Keerthikiran Komaravelli

Software Engineer

Andhra Pradesh, India7 yrs 1 mo experience

Highly Stable

Key Highlights

Expertise in ASIC design and SoC integration.
Specialized in end-to-end debug infrastructure.
Strong background in CDC and LINT analysis.

Stackforce AI infers this person is a Design Engineer specializing in ASIC and SoC integration within the semiconductor industry.

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Skills

Core Skills

Soc DesignCdcLint

Other Skills

system verilogverilog codingVerilog HDLC (Programming Language)Universal Verification Methodology (UVM)RTL Design

About

Design Engineer with expertise in ASIC design and SoC integration. Specializing in end-to-end debug infrastructure including CDC analysis, LINT analysis, validation support, and post-silicon bring-up across multiple project phases

Experience

7 yrs 1 mo

Total Experience

1 yr 9 mos

Average Tenure

2 mos

Current Experience

Cadence

Lead Design Engineer

Apr 2026 – Present · 1 mo · Hyderabad, Telangana, India

Intel corporation

SoC Design Engineer

Apr 2022 – Apr 2026 · 4 yrs · Hyderabad, Telangana, India

CDCsystem verilogSoC Design

Moschip

ASIC Design Engineer

Jan 2021 – Mar 2022 · 1 yr 2 mos · Hyderabad, Telangana, India

Institute of silicon systems pvt. ltd.

Trainee at Moschip Institute of Silicon Systems

Nov 2019 – Dec 2020 · 1 yr 1 mo

Amd

CO-OP Engineer, Client SOC RTL

Oct 2018 – Jul 2019 · 9 mos · Hyderabad Area, India

understood the significance of Clock Domain Crossing(CDC) and Power Aware CDC(CDC and PA-CDC) checks at RTL stage, various kinds of violations and solution for violations also familiar with various types of synchronizers and complete hands on experience working with mentor graphics questa CDC 0in tool for CDC analysis of SoC.
understood the significance of LINT checks. have complete Idea of rule set and how to perform it for a SoC
good understanding in verilog coding. can think of hardware for a module description not only logic.

CDCLINTverilog coding