Kiran Chinni — Director of Engineering
• 13+ Years of overall experience in Physical design, Synthesis, Static timing Analysis, Power-signoff(EM/IR), Physical verification, and Formal Verification. • Handled multiple tape-outs on RF, power management and LP3xDDR from long channel to cutting edge tech nodes(28 nm to 2nm) consisting of multi-million gates. working knowledge on SOC,NOC and AI chips. • Capable of managing and leading PnR and Signoff engineers across various programs. • Proficient in developing new methodology to improve the design/flow quality. • Experience in IP Integration for SOC and collaboratively work with DFT and DV teams in improving test time quality and validating timing. • Working with RTL teams on constraints develepoment. • Worked on multiple IPs across automotive and processor domains. • Quick learner with good analytical and problem solving skills. Specialties: - Place and Route - Synthesis - Static timing analysis - EM/IR and Signal Integrity Analysis - Formal verification - Physical Verification Tools : - ICC, ICC2, Fusion Compiler and Innovus - Synopsys Design Compiler, DC-topo - PrimeTime and Tempus - Synopsys formality, Library manager, milkyway env - Redhawk and Redhawk-SC - Mentor Calibre
Stackforce AI infers this person is a Semiconductor Physical Design expert with extensive experience in advanced technology nodes.
Location: Bengaluru, Karnataka, India
Experience: 14 yrs 4 mos
Skills
- Physical Design
- Soc
- Static Timing Analysis
- Timing Closure
Career Highlights
- Over 13 years of experience in Physical Design.
- Expert in managing PnR and Signoff engineers.
- Proficient in advanced technology nodes from 28nm to 2nm.
Work Experience
Alten
Associate Director-Physical Design - AlphawaveSemi (3 mos)
SOC PD Manager (Alphawave client) (1 yr 5 mos)
SOC- PD Manager(Samsung Semiconductor India Research ) (2 yrs 2 mos)
AMD
Member Of Technical Staff, Physical Design (2 yrs 3 mos)
Sankalp Semiconductor
Senior Physical Design Engineer (9 mos)
Wipro Limited
Senior VLSI Engineer (1 yr 1 mo)
Tata Consultancy Services
Design Engineer (2 yrs)
National Institute of Technology Silchar
Teaching Assistantat NIT Silchar (1 yr 9 mos)
Tata Consultancy Services
Systems Enginner (11 mos)
Assistant Systems Engineer (11 mos)
Assistant Systems Engineer Trainee (11 mos)
Education
Master of Technology (M.Tech.) at National Institute of Technology Silchar
Bachelor of Technology (B.Tech.) at Jawaharlal Nehru Technological University
Board of Intermediate Edducation at Nalanda Mahila Kalasala Vijayawada
SSC at Aditya High School