Sep 2013 – Jan 2015 · 1 yr 4 mos · BANGALORE (K.A.)

• QUALCOMM Bangalore since SEPT, 2013 – JAN, 2015:
• I am an experienced semiconductor professional with expertise in advanced technology nodes, including 14nm FinFET, 16nm FinFET, 20nm Bulk, and 28nm Bulk. At Qualcomm, I have been actively involved in the development of single and dual-port full-custom and semi-custom memory designs, including HPSP, LLPDP, LLSP, and STDSP, as well as ROM projects.
• My responsibilities span across various critical memory blocks such as Level Shifter, Local Data Path (LDP), Local Control (LBC), Clock Near/Far/Edge, Local Word Bitline Booster (LWBL), and Global Control + Pre-decoder (GBC). I have contributed to area optimization through custom cut reduction (Zero Padding), extraction at multiple technology nodes, and the generation of LEF files. Additionally, I have worked on Electromigration (EM) and IR Drop analysis, as well as the transition of single-port to dual-port custom memories, ensuring thorough verification processes.
• Passionate about circuit design and semiconductor innovation, I strive to optimize memory architectures for performance, power, and area efficiency while staying at the forefront of cutting-edge technology advancements.

Mar 2011 – Aug 2013 · 2 yrs 5 mos · Greater Noida

• STMicroelectronics Noida , Noida since MAR, 2011 – JUNE, 2013 :
• I am a semiconductor design professional with experience in memory development at STMicroelectronics, working within the TRnD group (MEMORIES). My expertise spans Single Port & Double Port (LVT, RVT, HVT, MVT, HS, LP, HD) SRAM and ROM memory development at advanced technology nodes (28nm, 32nm, and 28nm FDSOI).
• My work involves designing and optimizing key memory blocks, including I/O, row decoder, scan chain, and scan buffer. I have hands-on experience with new bit-cell library integration, layout design modifications, via-bar implementation, extraction, and verification across multiple process nodes. Additionally, I contribute to:
• Electromigration (EM) & IR Drop Analysis – Ensuring reliability for memory instances.
• Design Verification & Abstract Evaluations – Verifying designs with 14nm FinFET, 28nm, and 32nm DK.
• Technology Migration & Enhancements – Implementing feature updates and performance optimizations across multiple compilers.
• Physical Design & Layout Modifications – Addressing coordinate alignment, LG changes, pin height adjustments, and quality assurance for final product submission.

Jul 2009 – Sep 2009 · 2 mos · Noida, Uttar Pradesh, India

• I have hands-on experience in the full custom design flow using Synopsys tools, covering schematic entry, simulation, layout, RC extraction, post-layout simulations, and DRC/LVS verification leading to GDSII. As part of the Synopsys University Program, I successfully completed analog design labs and executed a Differential Amplifier design project from schematic entry to GDSII. Additionally, I documented the entire design process to ensure a comprehensive understanding of the workflow. My expertise lies in analog circuit design, verification, and layout methodologies, with a strong focus on precision and efficiency in advanced semiconductor technologies.

Aug 2008 – Oct 2008 · 2 mos · Noida, Uttar Pradesh, India

• During my internship at Virage, I gained hands-on experience in Standard Cell Library Development, working on both circuit design and layout activities. I successfully designed and implemented fundamental building blocks, including Inverter, NAND, and NOR gates, ensuring adherence to industry standards. Additionally, I developed a comprehensive tutorial on circuit design and full custom layout (covering DRC, LVS, parasitic extraction, and transistor matching considerations), which was well received and appreciated by my mentor.
• This experience has strengthened my foundation in analog and digital circuit design, layout optimization, and EDA methodologies, fueling my passion for advanced semiconductor design and automation.