Seshank Varma

Software Engineer

Hyderabad, Telangana, India12 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 5 years of experience in silicon design.
Expertise in ASIC and RTL development.
Proven track record in high-performance hardware solutions.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and SoC development.

Contact

seshankdendukuri2@gmail.com LinkedIn

Skills

Core Skills

Asic DesignRtl DevelopmentChip DesignDebuggingFpgaSoc DesignIp DesignVerificationAnalog Design

Other Skills

GPIO DesignValidationSynthesisUPF AutomationIP IntegrationNetwork IntegrationSystem VerilogLVSDRCParasitic ExtractionSpectre SimulationCLinuxModelSimSpyglass

About

With over 5 years of experience in silicon design and hardware engineering, I currently work as a Senior Silicon Design Engineer at Google. My role focuses on ASIC and RTL development, where I leverage deep expertise in Verilog and VHDL to contribute to efficient hardware design and verification processes. Collaborating with cross-functional teams, I aim to deliver high-quality and innovative silicon solutions. My prior experience as an ASIC RTL Design Engineer at Google and Senior Lead Engineer at Qualcomm allowed me to refine my skills in chip design, debugging, and hardware development. I am committed to supporting the creation of impactful, scalable, and high-performance hardware solutions that align with organizational objectives.

Experience

12 yrs 1 mo

Total Experience

2 yrs 5 mos

Average Tenure

3 yrs 6 mos

Current Experience

Google

2 roles

Sr . Silicon Design Engineer

Apr 2025 – Present · 1 yr 2 mos

ASIC DesignRTL Development

ASIC RTL Design Engineer

Dec 2022 – Apr 2025 · 2 yrs 4 mos

ASIC DesignRTL Development

Qualcomm

Senior Lead Engineer

Jun 2020 – Nov 2022 · 2 yrs 5 mos

Chip DesignDebugging

Xilinx

Senior Design Engineer

Feb 2019 – Jun 2020 · 1 yr 4 mos

ASIC DesignFPGA

Intel corporation

2 roles

SOC Design Engineer

Sep 2015 – Jan 2019 · 3 yrs 4 mos · Bengaluru, Karnataka, India

Project 1:
 Owning GPIO subsystem Design/Automation and wrapper logic implementation to SOC.
 Helping validation team to come up with test plan/ and also enabled jasper tool for gpio connectivity to IP’s.
 Strap logic design for GPIO PADS for Debugging.
 Supporting Synthesis team and BE team for appropriate design/Placement and timing closure.
 Supporting DFX team for the debug validation of GPIO controller and helping them understand the configuration required to make gpio work in dfx mode.
 UPF automation for GPIO controller and its corresponding components.
 IP Integration Owner for RTC, ITSS for SOC Integration.
 Understanding different interfaces for RTC, ITSS and successfully integrating it to SOC.
 Understanding of SOC architecture/Flows and Methodologies involved.
Project 2:
 Fabric/Network Generation and Integration for a complete SOC Die.
 Understanding various IP's connected to the Network and configuring the network accordingly.
 Integration of Fabric into SOC and debugging the basic test failures.
Learnings in this Role: A good understanding of PCI Express protocol.

GPIO DesignValidationSynthesisUPF AutomationIP IntegrationSoC Design+1

Graduate Technical Intern

Jun 2014 – May 2015 · 11 mos · Greater Bengaluru Area

IP Design and Verification:
> Clock Divider Block verification using System Verilog for Display IP.
> Test Suite Integration and validation of DisplayIP + Bridge Logic + External Controller.
> GLS simulation debug's for Display IP
> Running Regressions, creating report and debugging the failed test-cases.

System VerilogVerificationDebuggingIP Design