Amol Munde

Software Engineer

Bengaluru, Karnataka, India10 yrs 9 mos experience

Highly Stable

Key Highlights

Expert in VLSI design and verification.
Proven track record in semiconductor industry.
Strong educational background in VLSI-SD.

Stackforce AI infers this person is a semiconductor design engineer with expertise in VLSI and digital design.

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Skills

Core Skills

SystemverilogUpfLogic DesignFunctional VerificationEmbedded Systems

Other Skills

UFS 4.0/5.0 EnhancementUFS Performance ModelingUFSPerformance ModelingPCIE 4.0/5.0 DevelopmentPCIELow speed peripheral designI3CI2CUARTSPICANUFCS Charging ProtocolSERDES PHYRTL

About

Experienced Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Microsoft Word, UPF, SystemVerilog, Teamwork, and Matlab. Strong engineering professional with a Master’s Degree focused in VLSI-SD from National Institute of Technology Warangal.

Experience

10 yrs 9 mos

Total Experience

4 yrs 6 mos

Average Tenure

1 yr 9 mos

Current Experience

Synopsys inc

Sr Staff Engineer

Sep 2024 – Present · 1 yr 9 mos · Bengaluru, Karnataka, India · On-site

UFS 4.0/5.0 Enhancement to UFS controller.
UFS Performance Modeling

UFS 4.0/5.0 EnhancementUFS Performance ModelingSystemVerilogUPF

Qualcomm

2 roles

Senior Lead Engineer

Dec 2021 – Aug 2024 · 2 yrs 8 mos

PCIE 4.0/5.0 Development

PCIE 4.0/5.0 DevelopmentLogic DesignFunctional Verification

Senior Enginner(RTL Design)

Jul 2019 – Nov 2021 · 2 yrs 4 mos

Low speed peripheral design I3C,I2C,UART,SPI,CAN,UFCS Charging Protocol.

Low speed peripheral designI3CI2CUARTSPICAN+3

Intel corporation

2 roles

RTL Design Engineer

Jun 2016 – Jul 2019 · 3 yrs 1 mo

SERDES PHY (DP, eDP,MIPI,HDMI)
Hands on experience in all aspects of logic design like RTL,UPF,CDC, Timing constraints
etc. Closely worked with cross functional teams (Analog, physical design, silicon testing ,
verification etc) to ensure quality IP delivery
Worked for upf flow for digital partition of Display Phy, for handing multiple voltage
domain within this IP.
Responsible for RTL coding, Functional simulation, Integration of BMOD & SUB-IP,
Synthesize of various Digital Blocks.

SERDES PHYLogic DesignRTLUPFCDCTiming constraints+1

Intern

Jul 2015 – Jul 2016 · 1 yr

a) CDR Modeling: Clock and Data Recovery Circuit Modeling for Test bench reference model.
b) Regressions: Was responsible for daily regressions and code coverage metrics reports.
c) Doing formal property verification and writing reference Model
c)Assignments: a.UPF based multi-power domain design: Designed a simple 4-Power Domain digital circuit and wrote UPF for the design that involved isolation & retention cells and a level shifter. Simulated in VCS-NLP.
b.Asynchronous FIFO design: Wrote RTL and Testbench that included functional covergroups using System Verilog. Simulated using VCS™.

CDR ModelingRegressionFormal property verificationUPF based multi-power domain designAsynchronous FIFO design