Faizan Lone — Product Engineer
Experienced STA & Physical Design Engineer | 3+ Years in Timing Closure, ECOs & Advanced Nodes (28nm, 5nm,4nm) Skilled in static timing analysis, synthesis, floorplanning, I/O planning, PnR, and power/signal integrity optimization. Proven success in achieving timing, power, and area targets across 28nm, 5nm, and 4nm nodes. Adept at cross-functional collaboration with front-end and EDA teams to resolve complex challenges in advanced technology nodes.
Stackforce AI infers this person is a Physical Design Engineer specializing in advanced semiconductor technologies.
Experience: 3 yrs 7 mos
Skills
- Timing Closure
- Static Timing Analysis
- Physical Design
- Timing Analysis
Career Highlights
- 3+ years in advanced node physical design.
- Expert in timing closure and ECO generation.
- Strong collaboration with cross-functional teams.
Work Experience
Qualcomm
STA Engineer (2 yrs 4 mos)
AMD
Physical Design Engineer (1 yr 3 mos)
SION Semiconductors Private Limited
Physical Design Intern (6 mos)
Education
Master's Degree at Vellore Institute of Technology
Bachelor of Technology - BTech at Jawaharlal Nehru Technological University, Hyderabad
Class 10th at Burn Hall School