Sasikala Polu — Product Manager
Experienced Physical Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in RTL to GDSII,Synthesis flow,PnR flow, Low-power Design(UPF & CPF),LEC check,Lowpower LEC verify, basics of RTL Coding,Tclscripting ,shellscripting,INNOVUS tool ,GENUS tool,CONFRML tool, and Digital Electronics,. Strong engineering professional graduated from Maven silicon vlsi training center.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Low-power methodologies.
Location: Cuddapah, Andhra Pradesh, India
Experience: 7 yrs 7 mos
Skills
- Physical Design
- Low-power Design
- Silicon Design
Career Highlights
- Expertise in Physical Design and Low-power Design.
- Proficient in multiple EDA tools including Innovus and Genus.
- Strong foundation in Digital Electronics and RTL coding.
Work Experience
Cadence
Lead Design Engineer (8 mos)
AMD
Silicon design Engineer 2 (2 yrs 6 mos)
Sondrel Ltd
Senior Physical Design Engineer (1 yr 4 mos)
DXCorr Design Inc
Physical Design Engineer (3 yrs 1 mo)
Education
at Maven silicon vlsi training center
Bachelor of Technology at Krishna chaitanya Institute of Technology & Sciences, Jawayar nagar , MarkapurPIN-523316(CC-JU)
at NRI junior college in guntur
at Z.P.G.h schoool in kadapa
