Shweta Kumari — Software Engineer
As a DFT engineer with 3+ years of experience, I have a passion for ensuring the highest level of test coverage and quality for complex ASIC design. 1. Skilled in scan, ATPG, and GLS simulation, I have a proven track record of delivering test patterns on time and within budget. 2. My expertise in debugging complex test patterns and analyzing scan and ATPG results has enabled me to optimize test coverage and reduce test time, resulting in significant cost savings. 3. I am highly collaborative and thrive in cross-functional teams, with a strong ability to communicate complex technical concepts to stakeholders.
Stackforce AI infers this person is a DFT Engineer specializing in ASIC design and testing.
Location: Bengaluru, Karnataka, India
Experience: 5 yrs 11 mos
Skills
- Dft
- Gate Level Simulation
- Gls
Career Highlights
- Proven track record in delivering test patterns
- Expertise in optimizing test coverage and reducing costs
- Strong communicator in cross-functional teams
Work Experience
IBM
DFT Engineer (1 yr 8 mos)
Intel
Graphics Hardware Engineer (4 yrs 3 mos)
Education
M.Tech at Indian Institute of Technology, Kanpur
Bachelor of Technology - BTech at Institute of Engineering and Technology
