Sunil Gopanahalli Devaraj

CEO

Bengaluru, Karnataka, India13 yrs 8 mos experience

Highly Stable

Key Highlights

Led multiple successful tapeouts without timing issues.
Expert in high-speed DDR PHY designs and timing closure.
Trained juniors and conducted multiple STA training sessions.

Stackforce AI infers this person is a Semiconductor expert specializing in Static Timing Analysis and Physical Design.

Contact

Skills

Core Skills

Static Timing AnalysisSoc Sta

Other Skills

Timing closureBackend activitiesFloorplanPnRSignoffPlacementCTS specsTiming checksPre-Layout TimingCTS specSTA environmentTiming ECOsPower analysisLeakage recoveryScripting

About

Experienced ASIC STA-PD Lead with 11+ years of demonstrated history in working and leading teams for multiple Tapeouts. Key Skills are in Static Timing Analysis, SoC STA , Floorplanning , High Speed DDR Clock Methodology , Scripting and developing automations. • Expertise in STA concepts and Timing closure. • SoC STA Lead for Mobile SoC's at Gchips. • Responsible for complete STA-PD activities of PHY development. Lead the team comprising of Floorplan, PnR and signoff activities for multiple projects. • Worked on FloorPlan and PnR for the complex high speed LPDDR4 cores • Lead the STA efforts of Test Chip SoC’s with multiple IP and HM’s integration • Trained Juniors in the field of PD-STA and DDRPHY development • Handled multiple STA training sessions with audience comprising of Freshers till Executives • Knowledge of handling multiple tools : Primetime(SI,PX) , Innovus , Tempus , • Multiple Technical papers selected in various forums

Experience

13 yrs 8 mos

Total Experience

5 yrs 5 mos

Average Tenure

2 yrs 10 mos

Current Experience

Google

SoC STA Lead

Aug 2023 – Present · 2 yrs 10 mos · Bengaluru, Karnataka, India · On-site

Qualcomm

4 roles

Staff Engineer

Dec 2021 – Aug 2023 · 1 yr 8 mos

STA-PD Engineering Manager for LPDDR DDR-PHY’s.
Expertise in Timing closure for high speed DDRPHY designs.
Responsible for complete backend activities of PHY development. Lead the team comprising of Floorplan, PnR and signoff activities for multiple projects.
Worked with design teams to come up with strategies for timing closure of high frequency DDRPHY blocks
DDRPHY is a unique IP which multiple stake holders (packaging, analog IP, circuit simulation etc) . Worked with inter-disciplinary teams to achieve best PPA.

Timing closureBackend activitiesFloorplanPnRSignoffStatic Timing Analysis+1

Senior Lead Engineer

Promoted

Dec 2018 – Dec 2021 · 3 yrs

STA-PD Lead for LPDDR DDR-PHY's
Lead the team comprising of Floorplan, PnR and signoff activities for multiple projects.
Worked on FloorPlan and PnR for the complex high speed LPDDR4 cores.
Did Floor planning for the LPPDR5 DDRPHY’s to achieve best PPA’s even when non-scaling area trend was observed in prior chips
Worked with Design teams also to provide them feedback on design updates.

FloorplanPnRTiming closureStatic Timing AnalysisSoC STA

Senior Engineer

Dec 2016 – Nov 2018 · 1 yr 11 mos

STA Lead for LPDDR DDR-PHY's. Worked on multiple Generations of LPDDR.
Work with Physical Designers to come up with FloorPlan, Placement and CTS specs to meet Timing and complex skew and latency checks that are part of DDR Protocol
Work with Designers for Pre-Layout timing and for constraints validation/cleanup.
Worked on STA Convergence of multiple blocks of DDR PHY which includes the standard min,max,Timing DRC’s,Noise etc. DDR PHY also has skew checks and latency checks for the protocol to work, came up with scripts for newer Gen DDRPHY’s.
Created a Wrapper around the STA environment to make the regression faster and independent of user. This is used to run, collate the reports. This is being used by DDR PHY IP teams across globe in QCOM.
As STA lead for many Projects have successfully TO’ed ~10 Chips in 2 years without having a Timing issue in Silicon. Have handled multiple projects in parallel with my team
Trained Juniors in the DDR IP team in the field of STA.

FloorplanPlacementCTS specsTiming checksStatic Timing AnalysisSoC STA

Engineer

May 2015 – Nov 2016 · 1 yr 6 mos

STA Engineer for SoC Level and Block Level
Worked on Pre-Layout Timing to provide feedback to Designers for quality of the Synthesis
Worked with Physical Design Teams both Block Level and Top Level to come up with CTS spec.
Created Wrapper around the STA environment so that Block Owners without any STA knowledge can run STA for Blocks and generate ECO’s
Worked on SoC Level Timing Convergence.

Pre-Layout TimingCTS specSTA environmentStatic Timing AnalysisSoC STA

Lsi corporation

Synthesis & STA engineer

Jul 2012 – Apr 2015 · 2 yrs 9 mos · Bangaon Area, India

Responsible for analyzing pre-layout and post-layout timing, develop timing ECOs and leakage recovery ECO’s, and work closely with layout engineers to achieve timing closure.
Responsible for Power analysis and leakage current calculation of the SoC to be provided to tester teams. Work includes analysis of peak power, averaged power and leakage power, working with Verification/DFT to achieve power targets

Timing ECOsPower analysisLeakage recoveryStatic Timing AnalysisSoC STA