Rajat Jain

Product Engineer

India1 yr 6 mos experience

Key Highlights

Expert in ASIC and SoC verification methodologies.
Achieved 100% functional coverage in multiple projects.
Recognized for innovation in verification processes.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC and SoC methodologies.

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Skills

Core Skills

Functional VerificationUniversal Verification Methodology (uvm)

Other Skills

Sub system level VerificationDebuggingAssertion Based VerificationSystemVerilogTest PlanningDigital DesignsRALAPBVerilogDigital ElectronicsSystem on a Chip (SoC)DocumentationPlanningCC++

About

Currently working as Sr. Staff Engineer – Design Verification at Sivaltech, driving innovation in next-gen ASIC and SoC verification. Passionate about solving complex verification challenges and optimizing verification methodologies. 🚀 Protocol Knowledge: On-Chip Protocol- APB, AXI 4, MIPI -CSI | Networking Protocol- Ethernet IEEEE Standards: IEEE802.1 CB I work as a team player and take motivation and guidance from others to do MY BEST.

Experience

1 yr 6 mos

Total Experience

1 yr 6 mos

Average Tenure

Current Experience

Marvell technology

Contractor: Verification Engineer

Jun 2024 – Feb 2025 · 8 mos · Pune, Maharashtra, India · On-site

Project: RPM (Ethernet reconciliation PCS and MAC) | Scope: IP level Verification | Engaged in a contract role with Sivaltech.
Short Summary of Work:
Functional Coverage: Developed functional coverage from scratch for RPM, including MAC and CMR blocks. Conducted functional coverage analysis to achieve 100% coverage for the FPF milestone. (RPM200 and RPM USX)
Power Verification: Conducted power verification across four modes, providing insights to the physical design team.
Feature Verification: Verified background register access functionality and worked on CFA and ECC.
Team Collaboration: Facilitated team efforts in absorb, publish, and debugging activities.

Functional Verification

Infinera

Contract: Staff Verification Engineer

Jan 2024 – May 2024 · 4 mos · San Jose, California, United States · Remote

Project: Tahoe | Scope: Sub-chip & Full-chip Verification | Engaged in a contract role with Sivaltech.
Developed test cases from scratch to verify connectivity across all blocks in DT and GS, covering notification propagation, miscellaneous connectivity, notification statistics, programmable interrupts, and more.
Validated reset and clock connectivity across blocks to ensure proper functionality.
Designed and executed SLVERR testing for DT and GS blocks.
Verified register functionality in GS and DT blocks using RAL-based verification.

Universal Verification Methodology (UVM)

Amd

Contractor: Verification Engineer

Jul 2023 – Dec 2023 · 5 mos · Hyderabad, Telangana, India · On-site

Project: Telluride (T50, T20) | Sub-System level Verification | Engaged in a contract role with Sivaltech.
Integrated XAM (AXI) UVCs for ISP verification, connecting 6 UVC NMUs for end-to-end MIPI Rx VIP to DDR verification.
Developed Ethernet assertions for clocks operating at 1G, 2.5G, 5G, and 10G (Tx, Rx, and serial clocks).
Worked on PCIe EP and RC test cases for all DMA channels, including register configuration.
Created test cases for concurrent Ethernet (1G) and PCIe traffic.
Debugged NOC assertions to enhance system reliability.
Worked on the Ethernet scoreboard for VIP-to-DDR verification.

Universal Verification Methodology (UVM)Sub system level VerificationDebuggingAssertion Based Verification

Imagination technologies

Hardware Engineer 1

Oct 2021 – May 2023 · 1 yr 7 mos · Hyderabad, Telangana, India · Hybrid

Project: Ethernet Packet Processor(EPP) Verification | IP level Verfication |
Recognition: Received the Innovation Award at Imagination Technologies for exceptional contributions, as nominated by both the Safety team and management.
Short Summary of Work:
Register Map Verification: Developed and validated test cases for EPP registers, tables, and memory, including reserved space and address map randomization to ensure stability.
IEEE 802.1CB Standard Verification: Implemented test cases for Frame Replication and Elimination for Reliability (FRER), covering Talker, Relay, and Listener modes in Matched and Vector configurations.
Functional Coverage: 100% Functional Closure has been generated for the RTL verification sign-off.
Working on the bring-up for the MAC. I also Worked on ATI and ARI Interface for driving the packet.
Additional Responsibilities: Developed test cases for EMAC( Negative testing & other scenarios.), soft resets, and snake testing for all ports. Regularly updated RTL documents and collaborated with designers to debug and resolve RTL issues.
Worked on improving code coverage.
Developed, automated, and optimized multiple Python scripts for regression (customer side), register to debug, etc.

SystemVerilogFunctional VerificationDebuggingTest Planning

Maven silicon

Internship Trainee

Jul 2019 – Apr 2020 · 9 mos · Banglore

Universal Verification Methodology (UVM)Digital Designs

Avalanche infotech pvt. ltd

Summer Intern - VLSI

Jun 2018 – Aug 2018 · 2 mos · Indore, Madhya Pradesh, India

Made different digital circuits with the help of Verilog hardware descriptive Language
and hands-on with FPGA (Spartan 3 kit)

Indian institute of technology, bombay

Robotic competition

Jan 2017 – Dec 2017 · 11 mos · India

Indeyes infotech private limited

Industrial Training

Feb 2016 – Mar 2016 · 1 mo

Learned Microcontroller AtMega 16,
Electronics Circuits, Timers/Counters
Also worked on the Embedded system (AVR family) and made a real-time application based project.