V

Vivek T

Software Engineer

Bangalore Rural, Karnataka, India8 yrs 6 mos experience
Highly Stable

Key Highlights

  • 8 years of expertise in RTL design and low power methodologies.
  • Proven track record in power estimation and optimization.
  • Hands-on experience with leading semiconductor companies.
Stackforce AI infers this person is a Semiconductor Design Engineer with a focus on low power design and RTL integration.

Contact

LinkedIn

Skills

Core Skills

Low Power DesignRtl IntegrationPower EstimationUpf Design

Other Skills

QUALITY CHECKS5G Mobile Modem DesignLOW POWER METHODOLOGYUPF 2.x EnablementVerilogCadence Virtuososynopsis tcadC++ModelSimAltera QuartusField-Programmable Gate Arrays (FPGA)Analog Circuit DesignvcsApplication-Specific Integrated Circuits (ASIC)Perl

About

Front-end design engineer with 8 years of technical expertise on RTL design/integration and Low Power Design (UPF)/Power estimation and early power projections. Worked on mobile/CPU products. Possess comprehensive knowledge and experience in power optimization techniques, involves UPF design and RTL level power estimation using Power EDA tools (PA). Worked on RTL-lint CDC checks. Graduated in M.tech VLSI Design from VIT University and B.tech in ECE from KERALA University. I pursue new opportunities and can be reached either through this profile or by phone at 9080525464.

Experience

8 yrs 6 mos
Total Experience
2 yrs 10 mos
Average Tenure
--
Current Experience

Amd

Member of Technical Staff

Jan 2024 – Mar 2026 · 2 yrs 2 mos · Bengaluru, Karnataka, India · On-site

  • FEINT activities for Security IP, and SoC support.
  • End to end Low power design and quality checks for Client SoC programs.
  • RTL integration.
LOW POWER DESIGNPower EstimationRTL IntegrationQUALITY CHECKS

Qualcomm

Senior Lead Engineer

Oct 2022 – Jan 2024 · 1 yr 3 mos · Bangalore

  • Low power design and power estimation for DSP cores, early power projections.
  • BE low power quality checks
LOW POWER DESIGNPower EstimationQUALITY CHECKS

Intel corporation

3 roles

SoC Design Engineer

Promoted

Jun 2019 – Sep 2022 · 3 yrs 3 mos

  • RTL Integration+ UPF design. Worked on power management and ARM IPs and integration. Quality checks.
RTL IntegrationUPF DesignQUALITY CHECKS

Digital Design Engineer/low power design

May 2018 – Jun 2019 · 1 yr 1 mo

  • Worked on 5g mobile modem.
  • Design and integration of UPF.
UPF Design5G Mobile Modem Design

Intern

Jul 2017 – Apr 2018 · 9 mos

  • Was a part of low power methodology team,
  • UPF 2.x enablement across different tools.
LOW POWER METHODOLOGYUPF 2.x Enablement

Education

Vellore Institute of Technology

Master of Technology (M.Tech.) — vlsi design

Jan 2016 – Jan 2018

University of Kerala

Bachelor of Technology - BTech — Electronics and Communications Engineering

Jan 2010 – Jan 2014

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