Feb 2012 – Sep 2020 · 8 yrs 7 mos · Bangalore, India

• Led Systems Engineering & Product Development of storage products.
• Managed Complete Product System Architecture (includes SoC Architecture for Storage chips), Firmware schemes for Flash storage, Complete Product Development -Hardware (Components like ESD diodes, Power Management ICs, Buck Regulator and other generic LDOs, routing, form factor design, signal integrity), Substrate design, Board Bring up, Pre Tape out, Post Tape out and Product System Validation -FPGA based validation, BGA/real chip based validation (in MuB- in Mini Ugly Board or Evaluation Board), actual form factor based product validation with Software developed in house (FPGA based host with interface to driver and Python application/cases running on a PC).
• Was responsible to accomplish end to end Product line technology, execution and management for
• i. Hybrid storage based on Flash + Hard disk drive
• ii. SD, USB, NVMe based storage products (SD cards, M.2 and PCie based SSDs, USB sticks)
• iii. Performance, power , thermal calculation and optimizations at FW, HW and architecture level
• iv. Product development and certification for different markets like Automotive, Consumer, Industrial
• v. Prototype (Proof of concepts development) for various conferences like below (for 1TB SD card, world’s first SD form factor NVMe card).

Mar 2011 – Sep 2012 · 1 yr 6 mos · Bangalore Urban, Karnataka, India

• Worked on Fusion SoCs, System Verilog, OVM, Open Verification Components, SoC Verification, IP Verification and Validation activities.
• SoC integration for Fusion SoC – UNB + GNB into one SoC. Power, Thermal and Performance evaluation of SOCs
• Post acquisition of ATI, Canada, my team at AMD was responsible to verify and validate SOC Fusion of UNB and GNB in one chiplet and bring up IP verification, SoC verification, Performance evaluation, power aware verification/simulation.

Jul 2007 – Feb 2011 · 3 yrs 7 mos · Bangalore Urban, Karnataka, India

• Worked at client places like
• INTEL (DFT for SOC), MTU Aeroengines (DO-254 based IP development and Traceabilty to requirerments) and Nokia (Wireless Modem verification)

Feb 2006 – Jun 2007 · 1 yr 4 mos · Noida Area, India

• Responsible for Constrained Random Coverage Driven Verification , And ARM platform/SoC design and verification, Gate Level Verification, Formal Verification
• a. This was done for- Motorola Moto RAZR platform based on ARM
• b. Used Synopsys VIP (Verification IP) for ARM 1136/76 (AHB and AXI architectures) as Bus Functional Model (these are used to provide bus level commands or transactions to verify rest of the SoC platform and model/mimic ARM cores at interface level without actually having in brain in it
• c. Used ARM DSMs (Design Simulation Models System C)- ARM gives this as part of bundle when we buy ARM cores soft IPs. This was used to develop almost exact cycle accurate replica of the system (without actual synthesis of IP cores and ARM CPU cores in hardware level) to early validate algorithms, power, performance evaluations and thus necessary feedback to FW and SW to tune. This would save cycle time for later SOC design, Implementation, Verification, Pre TO and Post TO validation at FPGA/Emulation
• d. Used various IP, ASIC/SoC verification methodologies like AVM (Mentor Graphics), VMM (Synopsys), eVM -Specman (Cadence)- which later merged in to one UVM – Unified Verification Methodology.
• e. Used new verification concepts like Assertions, Coverage driven verification, 100% verification etc
• Done for Motorola Moto RAZR platform based on ARM (at Freescale, later NXP)

Sep 2002 – Feb 2006 · 3 yrs 5 mos · Pune Area, India

• RTL design for basic IPs
• 1394 Firewire -link layer, transaction layer and bridge design and verification, IP verification,
• SATA1.0a verification, SystemC, Verilog
• for 1394 serial interconnect (link layer) for SONY, Agere Systems (later LSI)