Narendra M Acharya

Design Manager

Bengaluru, Karnataka, India20 yrs 8 mos experience
Highly Stable

Key Highlights

  • Expert in RTL design and functional verification.
  • Led modem design projects at EdgeQ Inc.
  • Extensive experience in ASIC and SoC development.
Stackforce AI infers this person is a Senior ASIC and Modem Design Engineer with expertise in Telecommunications and Semiconductors.

Contact

LinkedIn

Skills

Core Skills

Rtl DesignFunctional Verification

Other Skills

RTL design using VerilogCoverage-driven verificationScripting in Perl/Awk/ShellDebuggingPHYICMicroprocessorsWireless BroadbandVerilogSoCASICDigital Signal ProcessorsPerlCFormal Verification

Experience

20 yrs 8 mos
Total Experience
4 yrs 9 mos
Average Tenure
1 yr 9 mos
Current Experience

Microsoft

Principal Design Manager

Sep 2024 – Present · 1 yr 9 mos · Bengaluru, Karnataka, India · Hybrid

RTL design using VerilogCoverage-driven verificationScripting in Perl/Awk/ShellDebuggingPHYIC+18

Edgeq inc.

2 roles

Member Of Technical Staff

Jan 2020 – Sep 2024 · 4 yrs 8 mos

  • Modem design.

Sr Principal Engineer

Jan 2020 – Sep 2024 · 4 yrs 8 mos

Nvidia

Senior ASIC Engineer

Mar 2013 – Jan 2020 · 6 yrs 10 mos · Bangalore

  • GPU PCIe and memory sub-system.

Broadcom communications

Senior Staff Design Engineer

Nov 2010 – Feb 2013 · 2 yrs 3 mos · Bengalooru

  • Broadcom acquired Beceem on November 2010.

Beceem communications

Design Engineer

Sep 2005 – Feb 2011 · 5 yrs 5 mos

  • Chip design

Education

Visvesvaraya Technological University

BE — Telecommunication

Jan 2001 – Jan 2005

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