Mangesh Potbhare — Software Engineer
4 years of experiences in Physical Design Engineer at Intel Technology Pvt. Ltd. • Hands-on experience in ASIC Block level Physical Design Flow (RTL to GDSII) - Synthesis, Floor planning, Placement, Clock Tree Synthesis, Routing and ECOs using DC, ICC2 and PT • Working experience with lower technology nodes 10nm and 10++nm • Experience in resolving various block level STA, Place and Route, DRC and LVS issues • Experience in working with fixing the Static, Dynamic and IR drop issues • Good understanding and experience in Tcl scripting • Knowledge in CMOS Fundamentals • Very committed and take any kind of new role and responsibility in PD domain
Stackforce AI infers this person is a VLSI design engineer with expertise in ASIC physical design and verification.
Location: Bengaluru, Karnataka, India
Experience: 9 yrs 3 mos
Skills
- Asic
- Physical Design
Career Highlights
- Expertise in ASIC Physical Design Flow from RTL to GDSII.
- Proficient in resolving complex block level issues.
- Strong commitment to taking on new responsibilities.
Work Experience
Qualcomm
Senior Physical Design Engineer (4 yrs 11 mos)
Intel Corporation
Graphics Hardware Engineer (4 yrs 4 mos)
Education
Master’s Degree at Shri Guru Gobind Singhji Institute of Engineering and Technology, Vishnupuri, Nanded
Bachelor’s Degree at Nagpur University
High School at Samarth Junior College Ramtek
X at M.H. State Board
