Harsha Ranjan Kumar

Software Engineer

Gaya, Bihar, India10 yrs 9 mos experience

Highly Stable

Key Highlights

10 years of experience in physical design.
Expertise in CPU subsystem design across multiple technology nodes.
Proficient in floorplanning, PnR, and timing closure.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in physical design and verification.

Contact

Skills

Core Skills

Static Timing Analysis

Other Skills

PrimetimePerlCTcl-TkSynopsys PrimetimeVerilogMatlabMicrosoft OfficeMicrosoft WordPowerPointPythonWindowsLinuxC++VHDL

About

Currently working at SiFive as senior staff engineer. Possess ~10 years of experience in physical design. Worked on physical design for CPU subsystem across multiple technology nodes and owned floorplanning, pnr , timing closure , Formal Verification and CLP of various CPU blocks.

Experience

10 yrs 9 mos

Total Experience

6 yrs 9 mos

Average Tenure

4 yrs

Current Experience

Sifive

2 roles

Senior Staff Engineer

Promoted

Apr 2025 – Present · 1 yr 2 mos · India

Staff Engineer

Jun 2022 – Apr 2025 · 2 yrs 10 mos · India

Qualcomm

5 roles

Senior Lead Engineer

Promoted

Dec 2020 – Jun 2022 · 1 yr 6 mos

Senior Engineer

Promoted

Dec 2018 – Nov 2020 · 1 yr 11 mos

Engineer

Promoted

Jun 2017 – Nov 2018 · 1 yr 5 mos

Associate Engineer

Jun 2015 – May 2017 · 1 yr 11 mos

Interim Intern

May 2014 – Jul 2014 · 2 mos · Bangalore, India

My project was on static timing analysis of the given netlist for which, I worked on PRIMETIME, a timing analysis tool of Synopsis. Another project was to write a perl script to compare two csv files containing several instances of the netlist and creating a separate output csv file containing the difference of entity values for each common instances in two files.

PrimetimePerlStatic Timing Analysis

Indian institute of technology, hyderabad

Research Intern

May 2013 – Jul 2013 · 2 mos · Hyderabad, India

My project was on bit error analysis for multiple relay networks in cooperative systems. The work involved exact Bit Error calculation through recursive algorithm using contour integral approaches.
With this, the BER calculation becomes less rigorous.