Preeti Singh

Software Engineer

Noida, Uttar Pradesh, India7 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

5+ years in low power design methodologies.
Expertise in advanced process nodes like TSMC 3nm.
Proficient in RTL design and static validation.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in low power methodologies and SOC design.

Contact

Skills

Core Skills

Rtl DesignLow Power DesignSoc DesignPhysical Design

Other Skills

CLPLow power SOC UPF modelingPower analysisStatic verificationLeakage estimationDesign ToolsLow power UPF/CPF FlowStatic validationScriptingEDA ToolsStatic Timing AnalysisUPFVclpEDAPerl

About

Dedicated professional, having 5+ years of working experience in Low power executions with Qualcomm Power design Team and Handoff to BE team(static validation /UPF Team) in Intel, Certified Post Graduation Advanced Diploma in ASIC Design and looking for career as Design Engineer in Semiconductor industry, which utilizes my all potential for organization as well as my personal growth.

Experience

7 yrs 10 mos

Total Experience

1 yr 11 mos

Average Tenure

3 yrs 1 mo

Current Experience

Qualcomm

2 roles

Senior Engineer

Dec 2024 – Present · 1 yr 6 mos · On-site

Developing and implementing low power design methodologies for compute level SOCs and Automobile chips, intricated with AI innovations.

RTL DesignCLPLow Power Design

ENGINEER II

May 2023 – Dec 2024 · 1 yr 7 mos · On-site

Involved in the power architecture and design of low power methodologies for advance process node (TSMC 3nm, 4nm).
Low power SOC UPF modeling.
Generating UPF using Qualcomm in-house Tool and validating with CLP Tool.
Leakage estimation for SOC using auto leakage flow and estimation on RBSC Mode.
Power analysis and compared the pre-layout and post-layout power numbers i.e internal, switching and leakage power.
Static verification of the RTL/Gate with UPF, debugged functional simulations and debugged Formality in context to LP features, Did power analysis on Gate level netlist and found ways to reduce power consumption.
Responsible for generating memories, power model, CPF and liberties using Qualcomm in-house Tool.
Worked on 3nm and 4nm advanced Technologies for compute chip, Mobile chip and Modem chip.
Tools – Prime Power/PTPX, VC-LP, VCS, VCS-NLP, Design Compiler, Formality, Memory Compilers from Synopsys , TSMC and ARM.

Low power SOC UPF modelingPower analysisStatic verificationLeakage estimationDesign ToolsLow Power Design+1

Intel corporation

RTL Design Engineer

Feb 2021 – Apr 2023 · 2 yrs 2 mos · Bengaluru, Karnataka, India · On-site

Low power UPF/CPF Flow.
Low Power Architecture and Design.
Low power SoC UPF modelling.
RTL design/release flows/infra (LINT, CDC, UPF)
Decent working knowledge in general scripting (Perl, Python etc.
Experienced in ASIC RTL design
Proven hands-on experience with SOC Design and IPs design
Create detailed micro architecture & implement complex IP or sub-system
Work with static validation team to debug and meet code coverage metrics
Experience in all design tools/standards/simulators like Lint, CDC, DC, VCS & UPF

Low power UPF/CPF FlowRTL designStatic validationScriptingRTL DesignLow Power Design

Rv-vlsi vlsi and embedded systems design center

Post Graduation (ADVANCED DIPLOMA IN ASIC DESIGN -- PHYSICAL DESIGN)

Oct 2019 – Nov 2020 · 1 yr 1 mo · India · On-site

Physical Design Training :-
Designing of ASIC block in 40nm Technology:-
Targeted concepts of Floor planning, metal layers, Power planning, Budgeting, Placement Optimization, Clock Tree Planning & Analysis, Scan Re-ordering, Clock Tree Synthesis, Routing, Parasitic Extraction, Static Timing Analysis, ECO tasks (timing & functional), DRC, LVS, Low Power Solution development & Implementation.
 EDA Tools - Synopsys IC compiler II, Prime time.
 Good knowledge in logic design, CMOS concepts.
Proficient in ASIC PD flow from Floorplan to GDS II with
various inputs at each stage.

Physical DesignEDA ToolsStatic Timing Analysis