Aug 2021 – May 2023 · 1 yr 9 mos · Bengaluru, Karnataka, India

Aug 2018 – Aug 2021 · 3 yrs · Hyderabad Area, India

• RTL design:
• L3 cache memory size changes and optimise for the designs targeted for desktop and laptop markets.
• Design changes to achieve low power at the core complex and fabric interface.

Aug 2014 – Jul 2018 · 3 yrs 11 mos · Bangalore, India

• RTL Design:
• Scale up SystemC based character OSD design to support higher resolution in a video scalar product.
• Shared SRAM controller design in a microcontroller chip with ARM Cortex M4 and Xtensa DSP
• System interconnect design for a Trustzone-M aware Cortex M33 based SoC
• Integration of legacy peripherals in Cortex M3 and Cortex M4F environments
• Others:
• Worked static timing analysis to replicate silicon violations
• Fix functionality issues using ECOs in a chip for metal tapeout
• Worked on full chip power analysis for an ARM Cortex M3 based SoC aimed to achieve lower digital dynamic power
• Automated power analysis flow and power report analysis using python
• General
• Helped new college grads and new employees to get started
• Took interviews for interns

Jul 2012 – Jun 2014 · 1 yr 11 mos · Mumbai

• Worked as Teaching assistant in
• Integrated Circuits Lab
• VLSI Design Lab
• VLSI Design Course

Jun 2011 – Jul 2011 · 1 mo · Bubhaneswar

• Automated the process of checking the status of various network nodes managed by Ericsson in Bhubaneswar and Cuttak using Excel VBA.