Shiva Kumar Bhavanari

Software Engineer

Hyderabad, Telangana, India8 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Creative problem solver with innovative approaches.
  • Strong collaboration skills, excelling in team environments.
  • Hands-on experience with ASIC verification and FPGA technologies.
Stackforce AI infers this person is a Semiconductor and Electronics Engineering professional with strong verification and validation skills.

Contact

Skills

Core Skills

FpgasAsic Verification

Other Skills

DDR memoriesDIMMsAHB protocolsAPB protocolsSEMI FORMAL VERIFICATIONClock GatingSPIQSPII2CSDMMCETHERCADENCEVERDISOCVNetwork

About

I'm an undergraduate student at BITS Pilani, actively searching for full-time opportunities in the field of Electronics. I'm currently interning at NVIDIA Graphics, Hyderabad from 3 months. My friends consider me highly creative who can be trusted to come up with new approaches. I can work alone well, however I'm at my best when I'm collaborating others. I can be reached either through this profile or by phone at 9948350385

Experience

8 yrs 10 mos
Total Experience
4 yrs 5 mos
Average Tenure
8 yrs 7 mos
Current Experience

Qualcomm

Senior Engineer

Nov 2017Present · 8 yrs 7 mos · Hyderabad, Telangana, India

Microsemi corporation

post silicon validation engineer(intern)

Aug 2017Nov 2017 · 3 mos · Hyderabad Area, India

  • Good knowledge of FPGAs.
  • Good knowledge of DDR memories,DIMMs, AHB,APB protocols.
FPGAsDDR memoriesDIMMsAHB protocolsAPB protocols

Nvidia

Intern

Jan 2017Jun 2017 · 5 mos · Hyderabad Area, India

  • I had done Internship at NVIDIA GRAPHICS Hyderabad in the Hardware Team as an ASIC Verification Engineer
  • I've done SEMI FORMAL VERIFICATION of SECOND LEVEL CLOCK GATING of I/O(SPI,QSPI,I2C,SDMMC,ETHER) IPs using CADENCE(Jasper Gold Tool) and done debug of Counter Examples generated by tool. Got Basic Idea about SPI,QSPI,I2C protocol.
  • SOCV (System On Chip Verification ) of PWM IP using VERDI tool.
ASIC VerificationSEMI FORMAL VERIFICATIONClock GatingSPIQSPII2C+4

Jsw energy ltd

Summer Intern

May 2015Jul 2015 · 2 mos · Vijayanagar

  • I've undergone basic Industrial training in Electrical department. I acquired sufficient practical knowledge on Transformers, Generators, Switch yard and Circuit Breakers.
  • I carried out a study project on Generators.

Education

Birla Institute of Technology and Science, Pilani

Bachelor of Engineering — Electrical and Electronics Engineering

Jan 2013Jan 2017

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