Vijay Kumar B T — CTO
7+ years of experience in the complete FPGA design cycle (design, simulation, synthesis, place and route, debug), FPGA Prototyping and debugging, Digital Design, RTL design, STA, timing closure, GCC, UPF.
Stackforce AI infers this person is a VLSI design expert with a strong focus on FPGA technologies.
Location: Bengaluru, Karnataka, India
Experience: 10 yrs 2 mos
Skills
- Fpga Prototyping
- Digital Design
Career Highlights
- Over 7 years of FPGA design cycle experience.
- Expertise in digital design and RTL design.
- Proficient in timing closure and static timing analysis.
Work Experience
Qualcomm
Lead Engineer Senior (1 yr 10 mos)
Synopsys Inc
Application Engineering, Staff Engineer (6 mos)
Application Engineer Sr I (1 yr)
Application Engineer II at Synopsys India (2 yrs 11 mos)
PathPartner Technology
VLSI Design Engineer (3 yrs 11 mos)
Education
Bachelor's degree at vtu
