Yogesh Sehrawat

Software Engineer

Bengaluru, Karnataka, India8 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

8+ years in ASIC design and micro-architecture.
Expertise in WLAN PHY hardware design.
Proven track record in RTL implementation and synthesis.

Stackforce AI infers this person is a Telecommunications and Networking expert with strong ASIC design capabilities.

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Skills

Other Skills

RTL DesignWiFiPHYDigital Signal ProcessingCVHDLVerilogMicrocontrollersMatlabVLSIElectronicsMicroprocessorsModelSimEmbedded SystemsCadence Virtuoso

About

ASIC Architect/Designer having 8+ years of experience developing micro architecture and RTL design of Wi-Fi (PHY) chipsets. Specialize in transforming complex wireless requirements into robust RTL designs, utilizing fixed-point and floating-point arithmetic. Experience of working on complex digital designs consisting of a million gates and up to 200k flops. Strong Wi-Fi domain knowledge with exposure to complete ASIC development cycle i.e., micro-architecture, RTL implementation, Lint, CDC, Synthesis, STA and coverage analysis.

Experience

8 yrs 9 mos

Total Experience

2 yrs 11 mos

Average Tenure

3 yrs 2 mos

Current Experience

Synaptics incorporated

2 roles

Staff Design Engineer

Mar 2025 – Present · 1 yr 3 mos · Bengaluru, Karnataka, India · Hybrid

WLAN PHY Hardware Design
RxFD Design Lead

Senior Design Engineer

Mar 2023 – Feb 2025 · 1 yr 11 mos · Bengaluru, Karnataka, India · Hybrid

WLAN PHY Hardware Design
Architecture/Design of RX sub blocks for IoT chipsets.

Qualcomm

2 roles

Senior Lead Design Engineer

Sep 2022 – Feb 2023 · 5 mos · On-site

WLAN PHY Hardware Design
TX (frequency domain) POC for 2nd generation STA and AP chipsets.
Responsible for block level design documentation and presentation, register set updates, timely RTL milestone releases and coordinating with cross functional teams.

Senior Design Engineer

Sep 2019 – Sep 2022 · 3 yrs · On-site

WLAN PHY Hardware Design
Architecture and design of TX frequency domain sub blocks for 802.11 be chipsets.
Designed a unified 802.11 a/n/ac/ax/be preamble generation unit supporting programmable preamble and RU tone map.
Architecture/Design of TX control path to enhance TX timeline budget.
Re-architected stream processing data path for area optimisation.
Responsible for RTL implementation, synthesis, end to end DV support, timing and coverage closure.

Juniper networks

ASIC Design Engineer II

Jul 2017 – Sep 2019 · 2 yrs 2 mos · Bengaluru Area, India · On-site

Network Switches Hardware Design
Block level design for network switch (L2) fabric.
Designed output traffic generator to serve incoming TDM data requests based on Ser-Des data rate.
Involved in design of traffic scheduler based on DWRR scheduling for load balancing across output ports.
Developed micro architecture from functional specifications with area and power optimisations.
Coded RTL and worked with DV team to develop test cases, debug and perform block level bring up.
Defined block level interfaces and register sets and implemented the same in RTL.