Sachin S

Product Manager

Bengaluru, Karnataka, India4 yrs 11 mos experience

Highly Stable

Key Highlights

5+ years in chip design verification.
Expert in UFS memory and Controller IP verification.
Strong background in formal verification methodologies.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in functional verification and design methodologies.

Contact

Skills

Other Skills

Formal VerificationUniversal Verification Methodology (UVM)Digital Image ProcessingSimulinkMATLABK-Nearest Neighbors (KNN)Arduino IDEvivadoWireless Communications SystemsSystemVerilog

About

5+ years of experience in chip design verification.Involved in IP/Subsystem functional verification

Experience

4 yrs 11 mos

Total Experience

4 yrs 7 mos

Average Tenure

4 mos

Current Experience

Amd

Sr.Silicon Design Engineer

Feb 2026 – Present · 4 mos · Bengaluru

Samsung semiconductor

2 roles

Associate staff engineer

Mar 2024 – Feb 2026 · 1 yr 11 mos

#UFS memory verification
#Controller IP functional verification

Senior Engineer

Jul 2021 – Mar 2024 · 2 yrs 8 mos

Samsung electronics

Intern

Feb 2021 – Jul 2021 · 5 mos · Bangalore Urban

Education

PES University

Bachelor of Technology — Electronics and Communications Engineering

Jan 2017 – Jan 2021

Stackforce found 100+ more professionals with Formal Verification & Universal Verification Methodology (UVM)

Explore similar profiles based on matching skills and experience

Rajendra Ranmale

Design Engineer, Senior Principal

at Broadcom

Bengaluru, India24 yrs 11 mos exp

VLSIMachine LearningSoCIntegrated Circuit DesignRTL design

Sharmila Mahimaidoss

Verification Leader

at Ericsson

Bengaluru, India18 yrs 11 mos exp

Functional VerificationProject Leadership

Melvin Balakrishnan

Senior ASIC Engineer

at NVIDIA

Bengaluru, India6 yrs 10 mos exp

Application-Specific Integrated Circuits (ASIC)RTL Design

Shradha Narayana Gowda

Pre Silicon Design Validation Engineer

at Intel Corporation

Dublin, Ireland6 yrs 10 mos exp

Pre-Silicon ValidationCross-team Coordination

Shreyas M O

Senior Silicon Validation Engineer (GPU/System)

at Qualcomm

Bengaluru, India2 yrs 9 mos exp

Pre & Post Silicon ValidationEmbedded SystemsIP verificationDigital ElectronicsVerification Methodologies

Saptamesh Shinde

Accumulated Expertise

at Career-Wide Experience

Mumbai, India0 mo exp

Aviral Shrivastava

Digital Design Engineer

at Analog Devices

Bengaluru, India10 mos exp

Digital DesignStatic Timing AnalysisSynthesis

Kirti Kansal

Senior Design and Verification Engineer

at Analog Devices

United Kingdom7 yrs 7 mos exp

Universal Verification Methodology (UVM)SystemVerilogFormal VerificationSystem on a Chip (SoC)