Pratheek PS

Product Engineer

Bengaluru, Karnataka, India1 yr 11 mos experience

Key Highlights

Expert in Verilog, SystemVerilog, and UVM methodologies.
Proven track record in achieving functional coverage closure.
Hands-on experience with Cadence JasperGold and mixed-signal verification.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in digital and mixed-signal design.

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Skills

Core Skills

Design VerificationUvmFormal VerificationMixed-signal VerificationVlsi Design

Other Skills

Python (Programming Language)Universal Verification Methodology (UVM)SystemVerilogCadence JasperGoldPythonBashTCLMakefilesVerilog-AMSMixed-Signal Integrated CircuitsDigital ElectronicsVerilogSoftware VerificationLinuxDesign Verification Testing

About

I’m a passionate and detail-oriented Design Verification Engineer with hands-on experience in verifying complex digital designs using industry-standard methodologies and tools. My expertise lies in Verilog, SystemVerilog, UVM, and Formal Verification using Cadence JasperGold apps. With a strong foundation in RTL design and verification, I specialize in building robust and reusable testbenches, driving functional coverage closure, and ensuring first-time silicon success. I bring deep tool expertise in: Cadence: SimVision, Xcelium, Verisium Debug, JasperGold Synopsys: Verdi, Design Compiler I thrive in collaborative environments, working closely with design, DV, and formal teams to deliver high-quality IPs and SoCs. My goal is to continuously evolve with the latest verification trends and contribute to building reliable and efficient silicon solutions. Let’s connect if you’re passionate about silicon design, verification innovation, or just want to talk tech!

Experience

1 yr 11 mos

Total Experience

1 yr 11 mos

Average Tenure

1 yr 11 mos

Current Experience

Skyworks solutions, inc.

2 roles

Design Verification Engineer 2

Apr 2026 – Present · 2 mos

Python (Programming Language)Universal Verification Methodology (UVM)Design VerificationUVM

Design Verification Engineer 1

Jun 2024 – Mar 2026 · 1 yr 9 mos

Responsibilities and Contributions:
Major Contributions :
1. Executed block-level functional verification using SystemVerilog and UVM
2. Achieved functional coverage and code coverage closure
3. Conducted full-chip testing for standard IPs including UART, SPI, and I2C
4. Performed formal verification using Cadence JasperGold apps for:
>FSM validation
>Connectivity checks
>Block-level functional correctness
Minor Contributions :
1. Improved Gate-Level Simulation (GLS) performance and debug efficiency
2. Developed default register testing strategies for analog-mixed signal (AMS) projects
3. Gained exposure to AMS verification methodologies and flows using Cadence Virtuoso
4. Created automation scripts and utilities using Python, Bash, TCL, and Makefiles to streamline verification workflows, simulation setup, and regression management

SystemVerilogUVMCadence JasperGoldPythonBashTCL+2

Cadence design systems

Product Validation Engineer

Nov 2023 – Jul 2024 · 8 mos · Bengaluru, Karnataka, India · On-site

Modeled Phase locked loop using Verilog-AMS (wreal) and SV-RNM (EEnet) .
Validated critical RNM feature with respect to Verilog - AMS, System Verilog and SV-RNM to check with the tool (Xcelium) compatibility.

Verilog-AMSMixed-Signal Integrated CircuitsMixed-Signal Verification

Maven silicon

VLSI Design and Verification

Jan 2023 – Oct 2023 · 9 mos · Banglore · Hybrid

Understood entire ASIC flow with respect to Design and Verification methodologies.
Got hands on experience with industry standard projects such as Router 1x3 and Serial peripheral interface (SPI).

Digital ElectronicsVerilogVLSI Design