Steve Zhang

Product Engineer

Kaohsiung City, Kaohsiung City, Taiwan2 yrs 9 mos experience

Highly Stable

Key Highlights

Expert in SRAM architecture and ASIC design flow.
Proven track record in reducing simulation cycles.
Strong collaboration skills across teams and time zones.

Stackforce AI infers this person is a Semiconductor Engineer with expertise in SRAM architecture and ASIC design.

Contact

[email protected]LinkedIn

Skills

Core Skills

Sram ArchitectureAsic Design FlowPower, Performance, Area (ppa) Optimization

Other Skills

Circuit AnalysisShell ScriptingMonte CarloSPICE SimulationDebuggingCollaborationIntrapersonal SkillsEDAWritten CommunicationData PrivacyData EntryConfidentialityCommunicationAttention to DetailTyping

About

Versatile Memory Compiler Engineer with strong background in SRAM architecture, SPICE simulation, ASIC design flow and full-stack compiler development. Specialized in debug workflows, timing path analysis, and automation of verification and characterization flows. Excellent in bridging schematic-level insights and layout implementations. Known for reducing simulation and debug cycles through script-based workflow integration and cross-team collaboration. Passionate about pushing PPA limits and delivering silicon-accurate results.

Experience

2 yrs 9 mos

Total Experience

2 yrs 9 mos

Average Tenure

2 yrs 9 mos

Current Experience

Synopsys inc

2 roles

Research And Development Engineer

Sep 2023 – Present · 2 yrs 9 mos · Hsinchu County, Taiwan, Taiwan · Hybrid

Led comprehensive SRAM bitcell analysis, including read/write margin, timing (Tcc, Tcq), power, and leakage analysis using XA/Monte Carlo Simulation for new and cross-compiler PDKs.
Proposed and implemented Engineering Change Orders (ECOs) to significantly improve Power, Performance, and Area (PPA) metrics by performing Inst_Eval and Inst_char, collaborating with the layout team.
Debugged and resolved complex Verilog simulation mismatches and functional failures in memory compilers, ensuring design integrity and consistency between schematic and behavioral models.
Performed comprehensive verification of circuit functionality using specialized checks, including cckerc, latchcheck, floatlockup, and hizcheck, ensuring robust design integrity.
Optimized memory compiler configurations (CAF files) to integrate new features and resolve circuit-level programming issues, enhancing design flexibility and performance.
Conducted in-depth waveform analysis using Waveview to identify root causes of simulation failures, including unknown states, signal integrity issues, and incorrect control logic.

Circuit AnalysisShell ScriptingSRAM ArchitectureASIC Design Flow

Intern

Jul 2022 – Jun 2023 · 11 mos · Hsinchu County, Taiwan, Taiwan · Remote

SRAM bitcell analysis and read/write margin analysis using XA
Create training material for the team
Collaborate with US engineer across time zones and help fixing the errors that netlist will encounter when the compiler is revised

Circuit AnalysisShell Scripting

Micron technology

Summer Intern

Jul 2021 – Aug 2021 · 1 mo · Taichung City, Taiwan

Data mining and data analysis
Use Python and Shell Script to implement automation tools, reduce the work time from days to minutes without losing accuracy

Intrapersonal SkillsEDA