Jan 2024 – Apr 2024 · 3 mos · Burnaby, British Columbia, Canada · On-site

• Participating DDR5 and CXL projects, developed scripts to automate the verification flow for employing DDR controller RTL components from third party to the testbench we employ.
• Analyzed verification results and ran regression through Cadence Verisium Manager. Updated release trackers and functional coverage.
• Utilized Cadence SimVision EDA tool for debugging and analyzing verification IPs in System Verilog.
• Modified existing UVM code to accommodate new verification requirements outlined in the test plan.

Sep 2023 – Dec 2023 · 3 mos · Burnaby, British Columbia, Canada · On-site

• Collaborating with cross-functional teams to ensure reliability of PCIe 4.0/5.0 switch applications, analyzing PCIe LTSSM and Ordered Sets to pinpoint hardware issues.
• Documenting Microchip ChipLink user manual, providing comprehensive instructions for customers and internal stakeholders on product usage and troubleshooting.
• Developing scripts in Python to automate debugging procedures and expedite result data processing.

Jun 2022 – Aug 2022 · 2 mos · Shanghai, China

• Responsible for the design, development, and implementation of a complete ATE-based test solution for new SOC(System on Chip) products using the Advantest V93000 test platform.
• Provide support to customers on debugging and resolving Advantest software and hardware issues, including digital-signal tests, mixed-signal tests, and High-speed signal tests.

Apr 2019 – Jun 2022 · 3 yrs 2 mos · Shanghai, China

• Mainly support for Chinese ICs customers’ test program development, and online debugging based on the V93000 tester, including Smartphone, PLC-IoT electric meter, Camera, and TCON (timing controller ) SOC Programs.
• Test method development for complex IPs in C++.