Gaddameedi Navya — Product Engineer
ASIC Physical Design Engineer with strong hands-on expertise in complete RTL to GDSII implementation flow. Proficient in floorplanning, placement, CTS, routing, STA, timing closure, and physical verification with a focus on achieving signoff-quality results. Experienced in industry-standard EDA tools including Synopsys ICC2, Cadence Innovus, Cadence Genus, and Synopsys Design Compiler. Strong exposure to 28nm and 32nm technology nodes with foundational knowledge of 45nm and 90nm processes. Skilled in timing-driven physical design, congestion analysis, power planning, and design optimization to achieve PPA (Power, Performance, Area) closure. Comfortable working in Linux environments with scripting knowledge in Tcl and Python for automation and debugging. Actively seeking full-time opportunities in ASIC Physical Design where I can contribute to real-time chip implementation, timing closure challenges, and advanced VLSI design flows in a high-performance semiconductor environment.
Stackforce AI infers this person is a VLSI Physical Design Engineer with strong expertise in semiconductor design and implementation.
Location: Hyderabad, Telangana, India
Experience: 5 mos
Skills
- Physical Design
- Vlsi Design
- Timing Closure
Career Highlights
- Expertise in RTL to GDSII implementation flow.
- Proficient in industry-standard EDA tools.
- Strong focus on achieving signoff-quality results.
Work Experience
Infosys Springboard
Digital Specialist
Takshila
Design Internship
Takshila Institute of VLSI Technologies
Physical Design Engineer (1 yr 11 mos)
Design Internship (5 mos)
Education
Bachelor of Technology - BTech at Sreenidhi Institute of Science and Technology
Class XII at sri chaitanya junior college
Class X at Krishnaveni Talent School - India