Santosh Salunke

Software Engineer

Maharashtra, India5 yrs 11 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in DFT and Silicon Design.
  • Proficient in library characterization and timing analysis.
  • Strong background in external IP onboarding.
Stackforce AI infers this person is a Silicon Design Engineer with expertise in DFT and library characterization.

Contact

LinkedIn

Skills

Core Skills

DftSilicon DesignLibrary Characterization

Other Skills

DFT TimingScan ATPGMBISTSTAExternal IP OnboardingStandard cell library characterizationspice simulationExternal IP onboarding

Experience

5 yrs 11 mos
Total Experience
3 yrs
Average Tenure
3 yrs 8 mos
Current Experience

Amd

2 roles

Sr. Silicon Design Engineer

Promoted

Apr 2025 – Present · 1 yr 2 mos

Silicon Design Engineer 2

Oct 2022 – Apr 2025 · 2 yrs 6 mos

  • DFT Timing, Scan ATPG, MBIST
DFT TimingScan ATPGMBISTDFT

Marvell technology

2 roles

Senior Engineer

Promoted

Jun 2021 – Nov 2022 · 1 yr 5 mos · Bengaluru, Karnataka, India

  • STA- Supported the CAD Methodology flow.
  • Library Characterization
  • External IP Onboarding
STALibrary CharacterizationExternal IP OnboardingSilicon Design

Hardware Engineer

Jul 2020 – Jun 2021 · 11 mos · Bengaluru, Karnataka, India

  • Standard cell library characterization, spice simulation to correlate the results.
  • External IP on boarding. (DDR PHY, USB, sensors etc)
Standard cell library characterizationspice simulationExternal IP onboardingLibrary Characterization

Education

National Institute of Technology, Tiruchirappalli

Master of Technology - MTech — VLSI System

Jan 2018 – Jan 2020

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