Shiva Kolli

Engineering Manager

Hyderabad, Telangana, India20 yrs 3 mos experience
Highly Stable

Key Highlights

  • Over 20 years in semiconductor engineering
  • Expert in IP development and program leadership
  • Proven track record in quality execution and compliance
Stackforce AI infers this person is a Semiconductor Engineering expert with strong program and release management capabilities.

Contact

Skills

Core Skills

Program & Release ManagementSemiconductor EngineeringProject ManagementEngineering ManagementStandard Cell LibrariesCircuit Design

Other Skills

Cross-functional Team LeadershipPVT SimulationsAnalytical SkillsMemory Compiler QAElectronic EngineeringMethodology & Quality GovernanceEngineeringIP Release ManagementProject PlanningScheduling ManagementResource PlanningProgram ManagementPeople ManagementStandard cell characterization and validationExtraction & Verification

About

I am an Engineering professional with more than 20 years of experience spanning IP development, standard cell design, memory compiler enablement, and advanced-node execution across global semiconductor organizations. My core expertise sits at the intersection of deep technical engineering and strategic program leadership, enabling me to deliver silicon-ready IP solutions while driving operational excellence and global release success. Over the course of my career, I have led the development and characterization of standard cell libraries from 90nm down to 7nm nodes, architected high-performance libraries optimized for area, leakage, and power, and supported memory compiler and automotive-grade IP qualification. I bring strong hands-on understanding of design, simulation, extraction, and PVT characterization complemented by the ability to govern releases, establish methodology improvements, and enforce cross-functional quality alignment. In my current role, I lead automotive memory qualification initiatives, improve compiler release methodologies, and collaborate closely with design, QA, and foundry engineering teams to strengthen IP quality and compliance. Prior to this, I managed global memory programs, serving as the single point of contact for release certification, customer qualification, and lithography sign-off, while driving multi-site execution and on-time delivery. What differentiates me is the combination of technical depth, program leadership, and a strong focus on quality execution enabling me to bridge engineering, release management, and business expectations effectively. I enjoy building methodology, solving complex engineering challenges, optimizing release processes, and partnering across global teams to deliver trusted IP at scale. I am passionate about developing high-quality semiconductor IP, supporting next-generation technology roadmaps, and enabling strong customer outcomes through reliable and performance-optimized solutions. 00009

Experience

20 yrs 3 mos
Total Experience
3 yrs 4 mos
Average Tenure
--
Current Experience

Synopsys inc

R&D Engineer, Staff

Feb 2020Jan 2026 · 5 yrs 11 mos · Hyderabad · On-site

Cross-functional Team LeadershipPVT SimulationsProject ManagementAnalytical SkillsProgram & Release ManagementSemiconductor Engineering+6

Invecas

2 roles

Project Manager

Jan 2017Feb 2020 · 3 yrs 1 mo · Hyderabad, Telangana, India · On-site

Project PlanningCross-functional Team LeadershipEngineering ManagementAnalytical SkillsProgram & Release ManagementSemiconductor Engineering+9

Senior Design Engineer

May 2015Jan 2017 · 1 yr 8 mos · Hyderabad, Telangana, India · On-site

Project PlanningCross-functional Team LeadershipStandard cell characterization and validationPVT SimulationsEngineering ManagementAnalytical Skills+14

Immensa semiconductors

Senior Design Engineer

Dec 2014May 2015 · 5 mos · Bangalore Urban, Karnataka, India · On-site

Cross-functional Team Leadershipstandard cell characterizationAnalytical SkillsSemiconductor EngineeringCadence SoftwareStandard Cell Libraries+4

Soft machines

Senior Design Engineer

Mar 2011Dec 2014 · 3 yrs 9 mos · Hyderabad, Telangana, India · On-site

Cross-functional Team LeadershipStandard cell characterization and validationPVT SimulationsExtraction & VerificationSemiconductor EngineeringCadence Software+5

Masamb electronics systems

Senior Design Engineer

Jul 2008Mar 2011 · 2 yrs 8 mos · Noida, Uttar Pradesh, India · On-site

standard cell characterizationElectronic EngineeringCircuit Design

Aurora’s techical research institute

Assistant Professor

Aug 2002May 2005 · 2 yrs 9 mos · Hyderabad, Telangana, India · On-site

Education

Osmania University, Hyderabad

Master of Technology - MTech — Radar Communications and Systems Technology

Jun 2005Jul 2007

VR Siddhartha engineering college

Bachelor of Technology - BTech

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