Srinadh Ponugupati — DevOps Engineer
I am an ASIC Design & Verification Engineer with hands-on experience in high-speed SERDES PHY verification, specializing in PMD layer verification for PCIe and Ethernet protocols. Currently at Synopsys, I work on 112G SERDES PHY verification, owning features end-to-end from test plan creation to regression and coverage closure. My core expertise lies in: SystemVerilog & UVM-based functional verification Constraint-random, coverage-driven verification Auto-Negotiation (IEEE 802.3), KR link training & datapath validation Regression debugging, root-cause analysis & interop verification I have successfully driven: Standalone testbench bring-up for SERDES PHY Change Order (ECO) feature verification Interoperability validation across multi-lane high-speed architectures Early issue detection during integration & simulation stages I bring strong foundations in: Digital Design Fundamentals Verification Plan Strategy Assertion-Based Verification Protocol-Centric DV Methodologies 🎯 Actively seeking Design Verification / SoC DV / IP DV roles in high-performance computing, networking, automotive, and processor-based SoC environments.
Stackforce AI infers this person is a Semiconductor Verification Engineer specializing in high-speed communication protocols.
Experience: 2 yrs 11 mos
Skills
- Systemverilog
- Uvm
- Functional Verification
- Eco Verification
- Interop
Career Highlights
- Expert in high-speed SERDES PHY verification.
- Proficient in SystemVerilog and UVM methodologies.
- Strong background in functional and coverage-driven verification.
Work Experience
Synopsys Inc
ASIC Design Verification Engineer (2 yrs 11 mos)
Maven Silicon
Digital VLSI Design and Verification Trainee (11 mos)
Education
Bachelor of Technology - BTech at Shanmugha Arts, Science, Technology & Reserch Academy (SASTRA), Thanjavur
