Revanth Mouli CL — Software Engineer

🔧 I turn circuits into stories — one transistor, one layout, one micron at a time. As an Analog & Mixed Signal Layout Design Engineer who thrives where precision meets creativity, I’ve spent the last 4+ years shaping VLSI integrated circuit & layout designs. began with a simple fascination for how memory signal paths flow across silicon — today, that fascination drives my work on complex architectures, clamp cells, SRAM bit-cells, mixed-signal macros, and next-gen high-speed interfaces. 🌟 Who I Am An engineer who doesn’t just place polygons — I solve problems, craft symmetry, optimize parasitics, and build layouts that stand strong under every PVT corner. 🔥 What I Bring to the Table ⚙️ Expertise in Analog & Mixed Signal Layout (A&MS) Designed, optimized & verified complex AMS blocks including clamps, decaps, DCD blocks, clock macros, and ESD structures. Delivered reliable analog & mixed signal layout design aligned with electrical, timing & reliability targets. 🔌 Strong VLSI Integrated Circuit & Layout Skills Deep understanding of CMOS fundamentals, electromigration, latch-up, antenna, IR-drop, parasitics, shielding, crosstalk, and device matching. Hands-on proficiency with Virtuoso, Custom Compiler, RCXTRA, EMIR, Calibre, PVS, Assura, StarRC. 🧠 Memory & Signal Architecture Expertise Designed full SRAM subsystems — 6T bit-cell, half-cell layout, row/column decoders, sense amps, precharge, control blocks. Characterized memory signal behavior across temperature and voltage variations. Applied advanced analog layout concepts — common centroid, inter digitization, dummy devices, guard rings. 🚀 Career Highlights ⭐ Synopsys — A&MS Layout Design Engineer Owned IO, clamps, and hard macro-level layouts for Platform Ucie GEN2. Built high-performance clamps with >100 µm² poly and optimized EMIR across critical cells. Improved safe operating area, solved electrical violations, and refined mixed-signal macro performance. ⭐ EpitomeCircuits — Analog & Memory Layout Design Engineer Completed end-to-end op-amp, ADC, DAC, and analog signal chain layouts with precision matching. Reduced IR-drop via optimized power mesh; minimized crosstalk with robust shielding. Delivered area-optimized VLSI integrated circuit & layout blocks with full DRC/LVS closure. Led the design of SRAM memory signal architectures, from bit-cell to peripheral circuits. 🎯 What I’m Looking For Opportunities where I can contribute as an Analog & Mixed Signal Layout Design Engineer and continue building innovative VLSI integrated circuit & layout solutions, & high-performance architectures.

Stackforce AI infers this person is a Semiconductor Layout Design Engineer specializing in Analog and Mixed Signal architectures.

Location: Mysore, Karnataka, India

Experience: 2 yrs 4 mos