Jun Cao

Director of Engineering

Los Gatos, California, United States25 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Director of R&D at Synopsys Inc.
  • Expertise in System on a Chip (SoC) design.
  • Over 17 years in semiconductor industry.
Stackforce AI infers this person is a semiconductor design expert with extensive experience in SoC and ASIC development.

Contact

LinkedIn

Skills

Core Skills

System On A Chip (soc)Semiconductors

Other Skills

Application-Specific Integrated Circuits (ASIC)VerilogIntegrated Circuits (IC)Embedded SystemsDebuggingField-Programmable Gate Arrays (FPGA)RTL DesignVery-Large-Scale Integration (VLSI)Integrated Circuit DesignArchitectureHardware ArchitecturePCIeARMLogic DesignStatic Timing Analysis

Experience

25 yrs 6 mos
Total Experience
8 yrs 6 mos
Average Tenure
9 yrs
Current Experience

Synopsys inc

Director, R&D

Jun 2017 – Present · 9 yrs · Mountain View, California

System on a Chip (SoC)SemiconductorsApplication-Specific Integrated Circuits (ASIC)VerilogIntegrated Circuits (IC)Embedded Systems+11

Marvell semiconductor

HW Architect SOC Platform Group

Oct 2005 – Jun 2017 · 11 yrs 8 mos

Broadcom

Principle Engineer

Dec 2000 – Oct 2005 · 4 yrs 10 mos

Stackforce found 100+ more professionals with System On A Chip (soc) & Semiconductors

Explore similar profiles based on matching skills and experience

SB

SNEHA BIRADAR

Accumulated Expertise

at Career-Wide Experience

Bijapur, India0 mo exp
PV

Pavithra Vinayagamoorthy

Senior Analog Layout Engineer

at SmartSoC Solutions Pvt Ltd

Bengaluru, India4 yrs 8 mos exp
Analog LayoutIC Layout
AP

Ankita Patel

Staff Engineer

at IBM

Bengaluru, India5 yrs 11 mos exp
Application-Specific Integrated Circuits (ASIC)Digital Electronics
CL

Changeun Lee

Application Engineer

at Synopsys Inc

Seongnam, South Korea26 yrs 2 mos exp
IntegrationTestingResearch and DevelopmentDevice Development
AA

Ashish A.

Director

at Asiclabs

Noida, India25 yrs 5 mos exp
Physical DesignSystem on a Chip (SoC)RTL DesignVerification
SS

Siva Somasundaram

Analog Layout Engineer

at leadIC Design Pvt Ltd

Erode, India4 yrs 9 mos exp
Analog LayoutCadence VirtuosoDesign Rule Checking (DRC)Layout Versus Schematic (LVS)Reliability Verification
GN

Gaidhani Nishant

AE Group Director

at Cadence

Bengaluru, India24 yrs 5 mos exp
Physical Design
Dhanuj Kumar Sharma

Dhanuj Kumar Sharma

Graphics Hardware Engineer

at Intel Corporation

Bengaluru, India3 yrs 10 mos exp
SoC IntegrationLPDDR5 IntegrationVerilogASIC design Methodology