Ankita Patel

Software Engineer

Bengaluru, Karnataka, India5 yrs 11 mos experience

Highly Stable

Key Highlights

Expert in PCIe subsystem design and integration.
Strong background in ASIC and digital electronics.
Proven leadership in complex engineering projects.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and PCIe technologies.

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Skills

Core Skills

Application-specific Integrated Circuits (asic)Digital Electronics

Other Skills

PCIeDebuggingTimingArchitectureDigital DesignsRTL CodingProblem SolvingInterpersonal SkillsMicroarchitectureIntellectual PropertyFunctional RequirementsLeadershipSystem on a Chip (SoC)SystemVerilogLint

Experience

5 yrs 11 mos

Total Experience

3 yrs 5 mos

Average Tenure

2 yrs 6 mos

Current Experience

Ibm

Staff Engineer

Dec 2023 – Present · 2 yrs 6 mos · Bengaluru, Karnataka, India · Hybrid

Owned end-to-end PCIe Gen5 EP and RC subsystem design, using synopsys PCIe ctrl and PHY, including
address map definition and architecture.
Led PHY bring-up and actively debugged link training, issues.
Delivered programming sequences and provided hands-on debug support for MSI-X, FLR, and SR-IOV.
Implemented PIPE-level muxing to enable bifurcation and aggregation.
Delivered SDC and provided support for timing closure.
Implemented RAS pipeline logic for vector processing unit (VPU):
Modulo-3 based RAS pipeline for add, subtract, and multiply vector instructions.
Parity-based RAS pipeline for permute, slide, and vector extension operations

PCIeDebuggingTimingArchitectureDigital DesignsApplication-Specific Integrated Circuits (ASIC)+1

Samsung semiconductor india research (ssir)

Associate Staff Engineer

Jul 2020 – Dec 2023 · 3 yrs 5 mos · Bengaluru, Karnataka, India

Owner of PCIe Sub-system in SoC
PCIe Subsystem involves Synopsys PCIe (Controller + PHY) integration along with custom logic. It Operates
in Dual mode and supports upto Gen 5 speed with 16 lanes & 1 link.PCIe Sub System has its own APB
bridge, APB to CRPARA bridge,sub controller, SYSREG and DFTMUX.
Come up with PCIe controller configurations based on customer requirements. Generated PCIe controller
RTL by setting configurations from Core Consultant tool(Synopsys).
Created architecture diagram, address mapping, Clock-sheet, reset sheet, memory sheet, etc.
RTL coding of MSI (Message Signaled Interrupt) module, APB to CRPARA module.
Provide Data path bring up sequence
Frontend activities - Module Integration, insertion of synchronizer /reset synchronizer, Lint, CDC, IP-XACT
flow etc.
Owner of PAD and DFTMUX modules in SoC
Created PAD sheet and DFTMUX sheet.
Generated PAD and DFTMUX RTL from existing scripts.
RTL generation, Compile and Lint