A

Ashish A.

CEO

Noida, Uttar Pradesh, India25 yrs 5 mos experience

Key Highlights

  • Expert in chip design with extensive leadership experience.
  • Proven track record in RTL design and physical implementation.
  • Strong background in managing engineering teams and projects.
Stackforce AI infers this person is a semiconductor design expert with extensive experience in chip development and engineering management.

Contact

LinkedIn

Skills

Core Skills

Physical DesignSystem On A Chip (soc)Rtl DesignVerification

Other Skills

Project ManagementVLSISoCASICVerilogMixed SignalSemiconductorsWirelessTimingProcessorsTCLICEDALow-power DesignStatic Timing Analysis

Experience

25 yrs 5 mos
Total Experience
4 yrs
Average Tenure
1 yr 10 mos
Current Experience

Asiclabs

Director

Aug 2024 – Present · 1 yr 10 mos · India · Remote

Synopsys inc

Design Services Manager

Sep 2022 – Nov 2024 · 2 yrs 2 mos · Noida, Uttar Pradesh, India · Hybrid

  • I am part of Synopsys Design Services Group and team works with almost all major chip design companies.
Physical DesignSystem on a Chip (SoC)Project Management

Asiclabs pvt ltd

Founder & CEO

Jun 2020 – Jan 2023 · 2 yrs 7 mos · Noida, Uttar Pradesh, India

Masamb electronics systems

2 roles

Director Of Engineering

Promoted

Jul 2018 – Dec 2019 · 1 yr 5 mos · Noida Area, India

Technical Consultant

Jul 2016 – Jul 2018 · 2 yrs · Noida Area, India

  • Provided consultancy in area of RTL Design, Verification and Physical Design, embedded design projects feasibility analysis etc.

Cadence design systems india pvt ltd

Engineering Director

Apr 2012 – Jun 2016 · 4 yrs 2 mos · Noida, UP, India

  • Manage a team responsible for Low Power, Mixed Signal and Advaced node RTL-2-GDS solutions validation

Intel

Engineering Manager

Jul 2004 – Feb 2012 · 7 yrs 7 mos · Bangalore, India

  • Responsible for managing team of physical Design experts for full chip RTL to GDS implementation.

Motorola (semiconductors poroducts group) india pvt ltd

Technical Lead

Mar 1998 – Jun 2004 · 6 yrs 3 mos · Gurgaon, Haryana, India

  • RTL-2-GDS block level execution for wireless and automotive chips.Technical Lead for full chip verification for Wirelss SOCs

Education

Indian Institute of Technology, Kanpur

B. Tech. — Electrical Enginerring

Jan 1991 – Jan 1995

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