Siva Somasundaram

Software Engineer

Erode, Tamil Nadu, India4 yrs 9 mos experience

Highly Stable

Key Highlights

Expert in analog and mixed-signal layout design.
Proficient in Cadence Virtuoso and advanced process nodes.
Strong background in reliability verification and ESD compliance.

Stackforce AI infers this person is a Semiconductor Layout Engineer with expertise in analog design and verification processes.

Contact

Skills

Core Skills

Analog LayoutCadence VirtuosoDesign Rule Checking (drc)Layout Versus Schematic (lvs)Reliability Verification

Other Skills

Electrostatic Discharge (ESD)Analog SemiconductorsVery-Large-Scale Integration (VLSI)CMOSIC LayoutRoutingPNREDAEmbedded CC (Programming Language)Linuxopenrail

About

VLSI Analog Layout Designer, designing and developing analog and mixed-signal layouts. Proficient in Cadence Virtuoso tool and methodologies, with integrity and passion for delivering high quality designs. Extensive knowledge of advanced process nodes, such as Samsung 8nm, intel 7nm, 5nm and basic knowledge in TSMC 7nm technologies.

Experience

4 yrs 9 mos

Total Experience

3 yrs 2 mos

Average Tenure

1 yr 7 mos

Current Experience

Leadic design pvt ltd

Analog Layout Engineer

Nov 2024 – Present · 1 yr 7 mos · Bengaluru, Karnataka, India · On-site

Analog LayoutCadence Virtuoso

Hcltech

Software Engineer

Sep 2021 – Nov 2024 · 3 yrs 2 mos · Hubli, Karnataka, India · On-site

Member of GPIO team, done with the Layout verification processes like DRC (Design Rule Check), LVS (Layout vs. Schematic), ERC (Electrical Rule Check), and HV (Openrail) cleanup in GPIO IPS. Worked actively with Design Engineers and executed the Layout specific critical constraints to meet timing, and performance specifications. Managed to clean ESD verification flows to meet the ESD requirements. Fixed Reliability Verification - EM, IR Drop and Antenna violations. Executed ECO implementation from scratch, both at the block level and overall CBB level, to resolve performance issues.

Design Rule Checking (DRC)Layout Versus Schematic (LVS)Electrostatic Discharge (ESD)Reliability Verification