Saurabh Arya

Software Engineer

Delhi, India15 yrs 10 mos experience

Key Highlights

Over 10 years in Verification IP development.
Expertise in UVM/System Verilog methodologies.
Key contributor to multiple VIP development teams.

Stackforce AI infers this person is a Verification Engineer with extensive experience in semiconductor and SoC industries.

Contact

Skills

Core Skills

SystemverilogUvm

Other Skills

LPDDREMMCSDAXIUSBUARTFunctional VerificationVerilogEDADebuggingSystem on a Chip (SoC)

About

Senior R&D Engineer having 10+ years of experience in UVM/System Verilog based Verification IP development, have been part of LPDDR/GDDR/SD/EMMC/USB2/USB3/AXI3/AHB/Interlaken/UART VIP development team.

Experience

15 yrs 10 mos

Total Experience

Average Tenure

Current Experience

Synopsys

3 roles

Senior R&D Engineer (Verification Group)

Promoted

Sep 2016 – Present · 9 yrs 9 mos · Greater Delhi Area

LPDDREMMCSDAXIUSBUART+7

R&D Engineer (Verification Group)

Promoted

Oct 2012 – Aug 2016 · 3 yrs 10 mos · Greater Delhi Area

Graduate Engineer Trainee(GET)

Sep 2011 – May 2012 · 8 mos

Samsung india software centre

Software Engineer SOC

May 2012 – Oct 2012 · 5 mos · Noida, Uttar Pradesh, India

Nsys design systems

Verification Engineer

Feb 2011 – Sep 2011 · 7 mos

Stag programming solutions ltd.

Trainee Engineer

Jul 2010 – Mar 2011 · 8 mos

Embedded systems software engineer

Education

BITS Pilani Work Integrated Learning Programmes

Master of Technology - MTech — Data Science

Aug 2018 – Feb 2020

IET, Alwar (University of Rajasthan)

Bachelor of Technology - BTech — Electronics and Instrumentation

Jan 2005 – Jan 2009

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