Aman C. — CEO
As a seasoned SoC/IP Verification Engineer with 10+ years of experience, I specialize in building robust, scalable, and standards-driven verification solutions for complex semiconductor designs. My career spans leading global organizations such as Synopsys, Cadence, Samsung, STMicroelectronics, Qualcomm, and Micron, where I have consistently delivered high-quality verification sign-off across SoC, IP, and VIP development environments. My expertise lies in System Verilog, UVM, Verilog, C, and protocol verification for I2C, I3C, SPI, SMBus, AMBA AHB/APB, combined with strong proficiency in tools like VCS, Questa, NCSIM, Verdi, IMC, V-Manager, Perspec, QSAM, and scripting with Perl/Shell. Over the years, I have driven end-to-end verification cycles from testbench architecture and testcase creation to coverage modeling, assertions, debugging, and closure. I have successfully led the enhancement and support of Synopsys VIPs, strengthened UVM frameworks at Cadence, delivered multiple SoC bring-ups, and achieved 100% toggle and functional coverage across diverse subsystems including RPM, interconnects, RCC blocks, and memory/peripheral components. My approach emphasizes quality, efficiency, and continuous improvement, ensuring reliable design validation and seamless collaboration with cross-functional teams. Enthusiastic about solving complex verification challenges, I thrive in fast-paced engineering environments where innovation meets precision. I bring a blend of deep technical expertise, customer-centric problem solving, and a consistent record of delivering high-impact verification outcomes. Skills: UVM | SystemVerilog | SoC Verification | IP Verification | VIP Development | Protocol Verification (I2C/I3C/SPI/AMBA) | Functional & Code Coverage | Debugging (Verdi) | Testbench Architecture | Regression Analysis | Automation (Perl/Shell)
Stackforce AI infers this person is a semiconductor verification expert with a focus on UVM and protocol validation.
Location: Bengaluru, Karnataka, India
Experience: 10 yrs 2 mos
Skills
- Functional Verification
- Universal Verification Methodology(uvm)
- Universal Verification Methodology (uvm)
Career Highlights
- Over 10 years of experience in SoC/IP verification.
- Expertise in UVM and System Verilog for complex designs.
- Achieved 100% toggle and functional coverage in diverse subsystems.
Work Experience
Silicon Patterns
Lead DV Engineer (2 mos)
Synopsys Inc
Staff Engineer (1 yr 11 mos)
SAE (1 yr 2 mos)
Cadence Design Systems
SE-II (1 yr 2 mos)
UST
Senior Engineer (7 mos)
Verification Engineer (7 mos)
Incise Infotech Private Limited
Verification Engineer I (1 yr 11 mos)
3ST Technologies
Intern (1 yr 5 mos)
Cadre Design Systems
FAE (1 yr 3 mos)
Education
Bachelor of Technology - BTech at KRISHNA ENGINERING COLLEGE, GHAZIABAD
Senior secondry (12th) at Rajkiya Pratibha Vikas Vidyalaya, Shalimar Bagh
Higher secondry (10th) at Rajkiya Pratibha Vikas Vidyalaya, Shalimar Bagh
