Shuvam Biswas — Software Engineer

ASIC Design Verification Engineer with 2.8+ years of experience in SystemVerilog and UVM-based verification environments, focused on verifying complex digital and high-speed interface blocks. Experienced in developing scalable verification environments, creating targeted test scenarios, and debugging RTL issues to achieve coverage closure and ensure design reliability. Currently working at Synopsys, contributing to the verification of the UPCS block, where I develop verification sequences, debug regression failures, and enhance testbench stability and reusability in UVM-based environments. I have contributed to multiple project releases by validating functional requirements and corner-case scenarios through structured verification methodologies. I also have hands-on experience in formal verification using VC Formal, including property development, constraint authoring, and formal convergence debugging. My work includes verifying critical UPCS behaviors such as data rate transitions, receiver detection, and power state sequencing, as well as performing Formal Connectivity Analysis (FCA) to ensure correct signal connectivity across design modules. In addition, I developed Python-based automation script to extract simulation coverage data and generate structured reports, improving visibility into verification metrics and regression tracking. I enjoy solving complex verification challenges and continuously improving verification methodologies to deliver robust silicon-ready designs. Core Expertise SystemVerilog, UVM Assertions (SVA) Functional & Code Coverage Formal Verification (FPV, FCA, FRV) VC Formal Python Automation VCS, Verdi Linux

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in digital design and formal verification.

Location: Kolkata, West Bengal, India

Experience: 1 yr 6 mos