Rakshith G R — Software Engineer
With over a decade of experience in engineering, currently contributing as a Principal Application Engineer at Synopsys Inc, specializing in SystemVerilog, UVM, and Unified Power Format (UPF). Collaborates effectively with teams to advance electronic design automation (EDA) solutions while ensuring robust verification methodologies. Committed to delivering impactful results aligned with Synopsys' mission to enable innovation in semiconductor design. Thrives in dynamic environments, leveraging technical expertise and problem-solving skills to optimize processes and support cutting-edge technology development.
Stackforce AI infers this person is a semiconductor design expert specializing in EDA and verification methodologies.
Location: Bengaluru, Karnataka, India
Experience: 11 yrs 11 mos
Skills
- Systemverilog
- Uvm
Career Highlights
- Over a decade of engineering experience
- Expertise in verification methodologies
- Strong collaboration in EDA solutions
Work Experience
Synopsys Inc
Principal Application Engineer (1 yr 7 mos)
Sr staff Application Engineer (11 mos)
Staff Application Engineer (1 yr 5 mos)
Senior Application Engineer 2 (2 yrs 4 mos)
Senior Application Engineer (1 yr 4 mos)
Mentor Graphics
Verification Technologist - Functional Verification (1 yr 6 mos)
Application Engineer 2 (7 mos)
Application Engineer (2 yrs)
Associate Application Engineer (1 yr)
Education
Bachelor of Engineering (B.E.) at Visvesvaraya Technological University
Secondary education at Carmel High School