Cirsambar Sainath — Software Engineer
RTL Design & Verification Engineer specializing in SystemVerilog-based design and AMBA protocol verification, currently working on networking datapath components including PFE, RDMA, GNIC adapters, and AXI4-Lite interconnects. Experienced in control-path RTL development, register access logic, and protocol-compliant integration for high-performance SoC systems. Core Expertise: • Verilog & SystemVerilog RTL Design • UVM-based verification environments • AMBA AXI / AXI4-Lite protocol implementation • Scoreboards & transaction-level checking • Functional coverage & SVA • FPGA validation using Xilinx Vivado (ILA/VIO) • SystemC modeling • PCIe architecture (TLPs, link training, packet flow) Passionate about building scalable verification environments and clean, reusable RTL architectures.
Stackforce AI infers this person is a Networking and SoC Design Engineer with expertise in RTL Design and Verification.
Location: Bengaluru, Karnataka, India
Experience: 3 yrs 9 mos
Skills
- Rtl Design
- Uvm-based Verification
Career Highlights
- Expert in SystemVerilog and UVM-based verification.
- Proficient in AMBA AXI and PCIe architecture.
- Skilled in building scalable verification environments.
Work Experience
Catalina Systems India Private limited
RTL Design and Verification Engineer (1 yr)
NATIONAL CADET CORPS - India
NCC CADET (2 yrs 7 mos)
Enquire Quiz Club NIT Calicut
Junior Executive (2 yrs 9 mos)
Education
Bachelor of Technology - BTech at National Institute of Technology Calicut