VIPUL KUMAR GANGWAR

Software Engineer

Kanpur, Uttar Pradesh, India2 yrs 6 mos experience

Key Highlights

Expert in RTL design and verification.
Hands-on experience with leading EDA tools.
Strong background in RISC-V architecture.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL design and verification.

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Skills

Core Skills

System On A Chip (soc)Logic Design

Other Skills

AMBALintCDCJasperGoldRISC-VRTL DesignRTL CodingMicro architectureRTL DevelopmentDigital ElectronicsVerilogComputer ArchitectureC++Python (Programming Language)Engineering

About

I'm working as a RTL Design Engineer in INCISE INFOTECH Pvt ltd where I worked on the LINT and CDC checks and synthesis in MIPI I3C design .Before that I worked in Proxelera pvt. Ltd. as an Intern VLSI Engineer where I worked on the design of RISC-V 5 stage pipelined architecture (32 bit). I have hands on experience in CADENCE JASPERGOLD,GENUS TOOL,SPYGLASS TOOL,XILINX VIVADO ,CONFORMAL TOOL. In my 2 years employment period I gained so many technical skills like LINT, CDC, LOGICAL SYNTHESIS LEC, AMBA PROTOCOLS (APB ,AHB ,AXI), COMMUNICATION PROTOCOLS (UART ,SPI,I2C,MIPI I3C).

Experience

2 yrs 6 mos

Total Experience

Average Tenure

Current Experience

Cadence

Design Engineer-II

Oct 2025 – Present · 8 mos · India · On-site

Qualcomm

Hardware Design Engineer -II (Temp)

Feb 2025 – Oct 2025 · 8 mos · Bengaluru, Karnataka, India · On-site

Worked on design enhancements and added new functionalities in IPs.
Worked on the Uflow and QA tests (PLDRC ,CDC,synth checks) of components.
Experienced in VC Spyglass for CDC/RDC and Lint checks.
Performed SOC-level CDC/RDC analysis (glitches, convergence, coherency, etc.).
Developed CDC/RDC timing constraints and debugged using Verdi.
Automated CDC/Lint dashboards and reporting via scripts.
Collaborated with Validation and R&D teams for issue resolution and quality checks.

AMBASystem on a Chip (SoC)

Incise infotech private limited

RTL Design Engineer - I

Dec 2023 – Oct 2025 · 1 yr 10 mos · Noida, Uttar Pradesh, India · On-site

Conducted Lint and CDC checks for the MIPI I3C Controller and Target using the JasperGold tool
Performed logical synthesis using TCL scripting and the Genus tool, optimizing the design for low power consumption and minimal area.
Carried out logical equivalence checking (LEC) using the Conformal tool.
Developed design code for Start and Stop bit detection, communication handling, clock generation with integrated clock gating cells, and implemented CRC5, CRC16, and CRC32 for error checking .

System on a Chip (SoC)Logic Design

Proxelera

VLSI Engineer

Jul 2022 – Dec 2023 · 1 yr 5 mos · Mysore, Karnataka, India · On-site

Led the RTL design efforts for a 5 stage pipelining RISC-V processor including the design of the datapath and control unit .
Designed and implemented the datapath to support R-type ,I-type ,S/B type ,U-type ,J-type instructions.
Active participation in team discussions ,providing valuable insights and contributing to problem solving sessions.

System on a Chip (SoC)Logic Design