Pawankumar Yendigeri — Software Engineer
Staff Engineer in ASIC Front-End Design, specializing in Micro architecture design, Synthesis and STA for high-speed interface IPs (MIPI PHYs). Skilled in designing constraints for High Speed SerDes designs using Synopsys tools like Fusion Compiler, PrimeTime, and TCM. Hands-on with Tcl, Shell, Python and flows involving CDC/RDC, formal checks, STA and DFT integration. Previously a Research Scholar at IIIT Hyderabad, working on hardware design and prototyping for customizable VR head-mounted devices. Passionate about timing-aware design, high-quality constraints, and efficient signoff correlation across front-end and back-end flows.
Stackforce AI infers this person is a Digital VLSI design expert with a focus on ASIC and hardware engineering.
Location: Hyderabad, Telangana, India
Experience: 3 yrs 4 mos
Skills
- Digital Vlsi Design
- Synthesis
Career Highlights
- Expert in ASIC Front-End Design and Micro architecture.
- Proficient in high-speed interface IPs and timing closure.
- Strong background in hardware design and prototyping.
Work Experience
Synopsys Inc
ASIC Digital Design Staff Engineer (1 yr 5 mos)
Senior Design Engineer (1 yr 11 mos)
Technical Intern (8 mos)
International Institute of Information Technology Hyderabad (IIITH)
Research Assistant (1 yr)
Jambhekar Automation Solutions
Hardware Intern (6 mos)
Education
MS by Research at International Institute of Information Technology Hyderabad (IIITH)
Bachelor of Technology at Vishwakarma Institute Of Technology
Global Internship program at Nanyang Technological University Singapore