Samrat Das — Software Engineer

I am a System & Formal Verification specialist with 10+ years of experience working on correctness and integration challenges across complex silicon systems. My work focuses on applying formal verification, CDC, low-power, and static analysis techniques to uncover deep design and integration issues—particularly in SoC interconnects, memory subsystems, datapaths, and protocol-heavy logic where simulation alone is insufficient. Across my roles at Synopsys and previously at Cadence, I have partnered closely with design and verification teams to diagnose complex failures, resolve formal convergence challenges, and translate tool results into actionable verification and design insights. I frequently operate as an escalation point for difficult correctness issues that span multiple blocks, clock domains, or power states. Rather than focusing on isolated block ownership, my strength lies in identifying what needs to be proven at the right level, shaping assumptions and abstractions, and aligning verification intent with real architectural behavior. This includes breaking down large verification problems, guiding formal-friendly design practices, and helping teams achieve meaningful confidence in system-level correctness. I specialize at the intersection of tools, methodology, and design intent, enabling teams to move beyond local closure toward robust architectural validation across complex SoCs.

Stackforce AI infers this person is a Semiconductor Verification Specialist with a focus on formal methods and system-level validation.

Location: Bengaluru, Karnataka, India

Experience: 10 yrs 7 mos