Shriram Gupta

Product Engineer

Mumbai, Maharashtra, India7 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in SoC design and power management.
Proficient in RTL coding and debugging.
Strong background in machine learning applications.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in SoC and power management solutions.

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Skills

Core Skills

Soc DesignPower ManagementRtl CodingPython (programming Language)

Other Skills

CDCDebuggingEmulationVerilogMachine LearningAnalytical SkillsApplication-Specific Integrated Circuits (ASIC)CC++TeamworkVerdiSystemVerilogConnectivity

About

Semiconductor industry is constantly evolving with new process nodes and architecture, enabled by engineers across the world. I aim to leverage this movement and my knowledge to design efficient chips that enhance the performance while reducing the chip cost and power consumption.

Experience

7 yrs 11 mos

Total Experience

3 yrs 11 mos

Average Tenure

5 yrs 11 mos

Current Experience

Intel corporation

2 roles

System-on-Chip Design Engineer

Jul 2020 – Present · 5 yrs 11 mos

Developing Power Management IP to optimize performance per watt for SoC Chip.
Enabled multiple IPs and core modules for active power management using Dynamic Voltage and Frequency Scaling (DVFS) technique.
Experience in SoC/Subsystem RTL integration flows with good understanding of CDC, Lint QC flows.
Developed SoC debug logic for visualizing internal signals of IPs to facilitate post-silicon debug.
Worked on SoC trigger fabric to throttle IPs and take snapshot of debug signal.
Possess a good understanding of Machine Learning, SoC Clocking/Reset/Debug Architecture, and CPU Microarchitecture.

CDCSoC designPower Management

Graduate Technical Intern

Jun 2019 – Jun 2020 · 1 yr

Utilized EFFM flow to verify RTL code compatibility with Emulation and FPGA platforms and provided assistance to emulation model team.
Developed a Python script to resolve Partition Hopping issue for Abutted Design, resulting in significant time and effort savings by eliminating 95% of redundant IO pins for derivative projects.

Reliance jio infocom limited

Radio Frequency Optimization Engineer

Aug 2015 – Aug 2017 · 2 yrs · Mumbai Metropolitan Region

Analyzed field coverage log file on X-cap vuze platform to extract various Radio Frequency parameters linked to single and multiple e-nodeb.
Generated a comprehensive report based on log analysis to identify physical alignment requirements for existing antenna and suggest new antenna to address coverage gaps.