KAVYA R

Software Engineer

Bengaluru, Karnataka, India9 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

9 years of expertise in ASIC digital design verification.
Led verification for functional safety and cybersecurity in Ethernet.
Contributed to OPEN Alliance test suite interpretations.

Stackforce AI infers this person is a highly skilled ASIC digital design verification engineer with a focus on automotive and Ethernet technologies.

Contact

Skills

Core Skills

VerilogVerification And Validation (v&v)

Other Skills

Micosoft ExcelTestingVerificationRTL validationVHDLFPGACadence VirtuosoXilinx ISEJavaC++MayaPowerPoint3D Studio MaxMicrosoft WordMicrosoft PowerPoint

About

I am an ASIC digital design verification engineer with 9 years of experience in Ethernet protocol. I work closely with RTL design team to converge on verification closure and guide other junior members in the team. Collaborates with other teams on effortless customer deliverables and releases. Verification lead of functional safety and Cyber security product line on Ethernet. Major contributions are done on OPEN Alliance test suit interpretations and corrections needed in 10baseT1S feature.

Experience

9 yrs 6 mos

Total Experience

6 yrs 5 mos

Average Tenure

8 yrs 10 mos

Current Experience

Synopsys inc

4 roles

ASIC Digital Design Engineer Sr staff

May 2026 – Present · 1 mo · Bengaluru, Karnataka, India

ASIC Digital Design Staff Engineer

Promoted

Mar 2024 – May 2026 · 2 yrs 2 mos · Bengaluru, Karnataka, India

Micosoft ExcelVerilog

ASIC Digital Design Engineer Sr I

Mar 2020 – Jun 2023 · 3 yrs 3 mos

Verification Engineer

Nov 2016 – Mar 2020 · 3 yrs 4 mos

Responsible for testing and verification of the systems used to develop or manufacture automobile products. We do analysis and verification to ensure the highest quality products.
Creates test plans for RTL validation, defining and running system simulation models and finding and implementing corrective measures for failing RTL tests.
Validating designs at block or full chip level by authorizing validation plans, writing focus tests, create event injectors, writing architectural and micro-architectural correctness checkers, developing BFMs (Bus Functional Model), running functional simulations and debugging failures.