Avinash Ranjan — Software Engineer
Skilled in CSR verification, mode transitions, interrupt and exception handling, Hypervisor/Virtual Supervisor mode CSR verification. Experienced in frontend pipeline (BTB, BPQ, RS, GHT) verification. Enhanced code coverage for Frontend unit of pipeline stage. Proficient in Verilog, System Verilog, UVM, functional coverage, assertions, and testbench development.
Stackforce AI infers this person is a CPU verification specialist in the semiconductor industry.
Location: Jamshedpur, Jharkhand, India
Experience: 4 yrs 6 mos
Skills
- Systemverilog
- Universal Verification Methodology (uvm)
Career Highlights
- Expert in CPU verification and frontend pipeline.
- Proficient in SystemVerilog and UVM methodologies.
- Strong background in digital design and verification.
Work Experience
Scaledge Technology
Senior CPU Verification Engineer (8 mos)
CPU Verification Engineer (4 yrs 6 mos)
Asic Verification Trainee Engineer (6 mos)
VLSIGuru Training Institute
VlSI Design and Verification Training (6 mos)
Education
Bachelor of Technology - BTech at NIST University
Matriculation and Intermediate at D.A.V Public School Nit Campus Adityapur Jharkhand
