Somnath Dey — Product Engineer
I am a Design Verification Engineer with 3.8+ years of experience in verifying complex digital and mixed-signal IPs using SystemVerilog and UVM methodology. I specialize in building scalable verification environments, developing comprehensive test plans, and driving verification closure across IP and testchip-level projects. Currently, I work on verification involving protocols such as JTAG/IJTAG, AXI, AHB, and APB, with hands-on experience in Gate-Level Simulation (GLS) and hardware emulation using Synopsys ZeBu. I have contributed to multiple projects involving testchip validation, glitch detection IPs, and AMS IP emulation enablement. I enjoy debugging complex design issues, collaborating with architects and RTL teams, and improving verification efficiency through automation and robust methodology practices. I am passionate about solving challenging verification problems and continuously learning new technologies in SoC verification and emulation.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in digital and mixed-signal IP verification.
Location: North 24 Parganas, West Bengal, India
Experience: 3 yrs 7 mos
Skills
- Emulation
- Universal Verification Methodology (uvm)
Career Highlights
- Expert in UVM and SystemVerilog methodologies.
- Proficient in building scalable verification environments.
- Strong background in SoC verification and emulation.
Work Experience
Synopsys Inc
Research And Development Engineer (2 yrs 5 mos)
Asiczen Technologies
Design Verification Engineer (1 yr 2 mos)
Education
Bachelor of Technology - BTech at Gandhi Institute for Education and Technology (GIET), Khurda, Bhubaneswar
Matric at DAV Public School