Aishwariya Vidhyasegar

Software Engineer

Austin, Texas, United States3 yrs 11 mos experience

Most Likely To Switch

Key Highlights

Expert in CPU physical design and verification tools.
Developed critical scripts for design reliability at Intel.
Innovative solutions for emergency vehicle traffic management.

Stackforce AI infers this person is a Semiconductor and Embedded Systems Engineer with a focus on design reliability and traffic management solutions.

Contact

Skills

Core Skills

Cdc Design CheckHigh Voltage Audit

Other Skills

Spyglass CDCCDCLintHigh Voltage design rule checksynchronizer audit scriptPythonSpectreCalibreVDC and VDR FlowOpenrail FlowPython (Programming Language)PerlCadence VirtuosoGEM5 SimulatorCadence InnovusSynopsys DC compiler

Experience

3 yrs 11 mos

Total Experience

11 mos

Average Tenure

2 yrs 3 mos

Current Experience

Intel corporation

CPU Physical Design Engineer

Mar 2024 – Present · 2 yrs 3 mos · Austin, Texas, United States

Synopsys inc

2 roles

Senior Application Engineer

Promoted

Feb 2024 – Mar 2024 · 1 mo

Applications Engineer II

Jun 2023 – Feb 2024 · 8 mos

Arizona state university

3 roles

Grader

Jan 2023 – May 2023 · 4 mos · United States

Grader for Computer Controlled Systems, Digital Design Fundamentals and Quantum Mechanics for Engineers course

Grader

Jan 2022 – May 2022 · 4 mos · United States

Grader for Photovoltaic Energy Conversion course

Grader

Jan 2022 – May 2022 · 4 mos · United States

Grader for Computer Controlled Systems

Intel corporation

Design Reliability Intern

May 2022 – Jan 2023 · 8 mos · Chandler, Arizona, United States

Developed the synchronizer audit script which identifies missing synchronizers, custom synchronizers, and illegal synchronizer cells, by analyzing the output file of Spyglass CDC and CDCLint tool.
Enabled CDC design check in the FE CDC Lint and performed analysis of meta-flop/CDC design structure with Synopsys Spyglass CDC tool.
Presented results driven in learning the basics of CDC synchronizers and CDC checker tool.
Evaluated risk assessment of device EOS/layout spacing with high voltage design rule check (DRC-runset) and performed front-end and backend High Voltage audit for
both intel tools as well as industry standard tool and followed-up with the design engineers.
Debugged the issues on synchronizer and HV audit script pointed by quality reliability engineers.

Spyglass CDCCDCLintHigh Voltage design rule checksynchronizer audit scriptCDC design checkHigh Voltage audit

Analog and digital labs india pvt ltd

Electrical Engineering Intern

Jan 2021 – May 2021 · 4 mos · Coimbatore, Tamil Nadu, India

Collaborated in a team of two and developed a smart emergency vehicle plan to help the ambulances reach the hospital on time thereby saving lives.
Controlled each traffic signal using raspberry Pi which is in turn connected to a centralized server.
Transmitted the parameters such as latitude, longitude, speed to the server when the ambulance starts, and calculated the distance and time at which the emergency vehicle will reach the nearest traffic signal and communicated to the controller so that of the signal so that it turns green as soon as the ambulance
approaches the signal.
Publication: https://ieeexplore.ieee.org/document/9489007