Jaswanth kumar yadlapalli — Software Engineer

> Worked on different Technologies such as TSMC 140nm, 28nm,5nm GPDK 45nm 90nm, GF 22 nm, Intel 22nm(16LTLT),SS14nm >Worked on GPIO from block level to Top Level >Worked on blocks like RX , TX(driver, predriver) ,HBM,OP Amp,LDO, PowerManagement > Worked on Project based on IO,Memory IO with GPIO. > Efficient in physical verification using Calibre PVS and ICV. > Worked on Block level to Top level Floor plan, Placement and Physical Verification. > Understanding signal flow to acquire an optimum floor plan and power plan. > Good understanding of chip failure mechanisms like Antenna, Latch up, EM . > Knowledge on concepts like Matching, well proximity, STI, Double pattern Lithography. > Communicating with Designers, and suggesting the best layout to meet the spec > Delivered Quality Layouts in time to meet customer schedules. > Passion to learn and adapt new tools and methodologies.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in layout and physical verification.

Location: Vijayawada West, Andhra Pradesh, India

Experience: 5 yrs 7 mos