A

Anshul Garg

CTO

Noida, Uttar Pradesh, India9 yrs 3 mos experience

Key Highlights

  • Experienced in memory design and characterization.
  • Strong background in digital and analog electronics.
  • Proficient in Perl automation and layout design.
Stackforce AI infers this person is a Memory Design Engineer with expertise in VLSI and semiconductor industries.

Contact

LinkedIn

Skills

Other Skills

Digital ElectronicsAnalog CircuitsSemiconductorsRoboticsLinuxperllayoutCharacterizationcmosPerl AutomationMicrosoft Excel

Experience

9 yrs 3 mos
Total Experience
--
Average Tenure
--
Current Experience

Stmicroelectronics

Technical Leader

Mar 2023 – Present · 3 yrs 3 mos · Greater Noida · On-site

Synopsys inc

2 roles

R&D Engineer Sr1

Promoted

Nov 2021 – Mar 2023 · 1 yr 4 mos · Noida, Uttar Pradesh, India

R&D Engineer II

Apr 2019 – Nov 2021 · 2 yrs 7 mos · Noida, Uttar Pradesh, India

  • Working in Memory design.

Arm

Design Engineer (consultant)

Jan 2018 – Mar 2019 · 1 yr 2 mos · Bengaluru Area, India

  • Worked in standard cell characterization.
  • Generation and Validation of All the views.

Sankalp semiconductor pvt ltd

Design engineer

Feb 2017 – Mar 2019 · 2 yrs 1 mo · Bengaluru Area, India

  • Got trained in deeper VLSI concepts.
  • Completed Project on SRAM circuit design and layout as a part of training.

Education

Jaipur Engineering College and Research Centre (JECRC)

Bachelor of Technology - BTech — Electronics and Communication Engineering

Stackforce found 100+ more professionals with Digital Electronics & Analog Circuits

Explore similar profiles based on matching skills and experience

MA

Mazumdar Anirudh

ASIC Digital Design Engineer

at Synopsys Inc

Hyderabad, India2 yrs 7 mos exp
LA

Lukman A R

ASIC Digital Design Staff Engineer

at Synopsys Inc

Bengaluru, India5 yrs exp
GN

Gunturi Venkata Nikhil

Asic Digital Design Sr Engineer

at Synopsys Inc

Hyderabad, India2 yrs 9 mos exp
Digital DesignEmbedded Systems
BS

Bhargav S

Senior ASIC Design Engineer

at Qualcomm

Bengaluru, India3 yrs 11 mos exp
5G New Radio (NR)ModemsLow powerVLSILogic Design
AP

ABHISHEK PANDEY

R&D Engineer (Memory Design )

at Synopsys Inc

Patna, India3 yrs 6 mos exp
Analog Circuit Design
ST

Sabiha Tanveez

Asic Digital Design, Senior Engineer

at Synopsys Inc

Bengaluru, India3 yrs exp
RTL DesignDFT
HN

Hemakalash M Naik

A&MS Layout design, sr Engineer

at Synopsys Inc

Bangalore Urban, India3 yrs exp
A&MS layout designDigital IC DesignPhysical Verification
CH

Chetana Harapanahalli

Lead Design Engineer

at Cadence Design Systems

Bengaluru, India9 yrs 9 mos exp
DesignSemiconductor Industry