Aviral Singh

Software Engineer

Noida, Uttar Pradesh, India6 yrs 4 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Recognized for customer release migration under tight timelines
Quarterly Award for VC SpyGlass Lint design intent testing
Execution Excellence Award for deploying VC SpyGlass Lint at scale

Stackforce AI infers this person is a VLSI verification engineer with expertise in static sign-off and quality improvement.

Contact

Skills

Core Skills

Verification And Validation (v&v)Rtl SignoffVc SpyglassStatic VerificationProduct Validation

Other Skills

LintCDCSynthesisVerdiSpyglassRTL DebugDigital ElectronicsVerilogSystemVerilogStatic Timing AnalysisDigital Circuit DesignC (Programming Language)BashTCLC++

About

I’m a Staff Engineer in Synopsys’s EDA group with 4+ years of experience in verification and validation, focused on static sign-off for SoC/RTL designs. I specialize in LINT and CDC using VC SpyGlass, working with R&D, field, and customers to improve QoR, tighten releases, and catch issues before they reach production. My work spans design intent testing, on-site validation on large RTL, static verification across SOCs/IPs, and scripting in Tcl/Bash, with tools across the SpyGlass / Verdi ecosystem. Key Highlights: • Recognition for customer’s release migration under tight timelines and for closing QoR gaps with clear documentation. • Quarterly Award for VC SpyGlass Lint design intent testing supporting smooth adoption. • Execution Excellence Award from the field team for deploying VC SpyGlass Lint at scale with key customers. • I also hold a granted patent (IN 202011026118 — Water Management System). I’m motivated by deep, quality-focused problems in VLSI verification. Outside work, I enjoy music, food, and travel.

Experience

6 yrs 4 mos

Total Experience

3 yrs 2 mos

Average Tenure

4 yrs 7 mos

Current Experience

Synopsys inc

4 roles

Staff Engineer

Apr 2026 – Present · 2 mos · Noida, Uttar Pradesh, India

VC SpyglassVerification and Validation (V&V)RTL SignoffLintCDCSynthesis+18

Senior Engineer, Validation/Verification

Promoted

Jan 2024 – Apr 2026 · 2 yrs 3 mos · Noida, Uttar Pradesh, India

Own static sign-off and customer-facing validation for complex RTL using VC SpyGlass and related flows.
→ Lead design intent testing and on-site validation on large RTL for strategic customers
→ Drive QoR improvements and clear performance analysis for high-stakes releases.
→ Partner with R&D, field, and customers to close gaps in LINT/CDC methodology, constraints, and flow issues before they impact production schedules.
→ Analyze design goals and specifications to anticipate failure modes, document findings, and raise fixes that improve reliability at scale.

RTL SignoffVerilogSystemVerilogLintCDCSpyglass+6

Applications Engineer I

Oct 2021 – Dec 2023 · 2 yrs 2 mos · Noida, Uttar Pradesh, India

Delivered static verification support and product adoption for VC SpyGlass–based LINT and CDC flows across customer SOCs/IPs.
→ Executed static verification (LINT, CDC) on customer SoC/IP designs; triaged violations, root-caused flow issues, and aligned on sign-off criteria with design teams.
→ Supported customer deployments of VC SpyGlass Lint: test planning, methodology guidance, and hands-on debugging with field and R&D.
→ Contributed to on-site testing and release-hardening activities focused on QoR and consistent results across design styles and revisions.

VC SpyglassLintCDCVerilogTCLSpyglass+3

Intern (Product Validation)

Aug 2021 – Oct 2021 · 2 mos · Noida, Uttar Pradesh, India

Product validation internship focused on VC SpyGlass Lint quality, test planning, and documentation.
→ Helped develop test plans to validate product changes and strengthen VC SpyGlass Lint internal regressions.
→ Supported updates to user-facing documentation used for customer and field enablement.
→ Built hands-on familiarity with LINT flows, scripting (Tcl), and validation practices in a production EDA environment.

LintTCLUnixProduct ValidationVerilogDigital Electronics+2

Pine training academy

3 roles

Design and Verification Trainee

Aug 2020 – Jul 2021 · 11 mos

Covered following modules-
✓ C and C++
✓ Digital Electronics
✓ Verilog
✓ SystemVerilog
✓ STA Basics
✓ UNIX commands and Bash

Digital Design Trainee

Jan 2020 – Jul 2020 · 6 mos

Learned Hardware Description Language Verilog, Learned to design Combinational and Sequential Digital Circuits using Verilog Coding on Xilinx ISE.

Digital Hardware Trainee

Aug 2019 – Dec 2019 · 4 mos

Learned to design Combinational and Sequential Digital Circuits using Schematic Design on Xilinx ISE.

Sapro electronics & electricals (india) private limited

Trainee

Aug 2018 – Sep 2018 · 1 mo · Ghaziabad

Learned Embedded Cum Autonomous Robotics and also have hands-on experience on ATMEGA-16 microcontroller and it's interfacing with various sensors and devices.