Prakhar Srivastava

Software Engineer

Noida, Uttar Pradesh, India3 yrs 8 mos experience
Highly Stable

Key Highlights

  • 4+ years in full-custom SRAM layout at advanced nodes.
  • Expertise in DRC/LVS closure and PPA optimization.
  • Skilled in cross-domain collaboration with circuit design teams.
Stackforce AI infers this person is a Memory Layout Engineer with expertise in advanced semiconductor design.

Contact

LinkedIn

Skills

Core Skills

Memory Layout DesignPlacement & Routing

Other Skills

Memory Architecture-Single/Dual portFloorplanningFull Custom LayoutLayout Versus Schematic (LVS)Design Rule Checking (DRC)Layout DesignCMOSVery-Large-Scale Integration (VLSI)Custom CompilerLinuxPython (Programming Language)Microsoft PowerPointProduct DevelopmentResearchEngineering

About

Memory Layout Engineer with 4+ years of experience in full-custom SRAM layout at advanced nodes (A14, 2nm, 3nm, and 22nm). Skilled in Periphery logic design (Centres, lOs etc.), DRC/LVS closure, ERC/DFM compliance, Rescheck, PPA optimisation, Matching and Shielding.Experienced in Synopsys Custom Compiler layout, ICV verification, and cross-domain collaboration with circuit design teams.Keen to expand into Memory Layout/ Compiler development and flow automation/ Physical Design roles.

Experience

3 yrs 8 mos
Total Experience
3 yrs 8 mos
Average Tenure
3 yrs 8 mos
Current Experience

Synopsys inc

2 roles

Layout Design, Engineer

Oct 2022 – Present · 3 yrs 8 mos

Placement & RoutingMemory Layout Design

Technical Intern

Feb 2022 – Oct 2022 · 8 mos

Education

Noida Institute of Engineering & Technology

Bachelor of Engineering - BE — electronics and communication engineering

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